Ujjwal Guin

Assistant Professor
Department of Electrical and Computer Engineering
Auburn University
325 Broun Hall, Auburn, AL 36849-5201, USA
Email: ujjwal.guin at auburn dot edu
Phone: (334) 844-1835 (Office)
[Curriculum vitae][Google Scholar][Research Gate]


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Books
  1. M. Tehranipoor, U. Guin, and D. Forte, "Counterfeit Integrated Circuits: Detection and Avoidance", Springer, 2015, [Amazon] [BibTeX: tehranipoor2015counterfeit].
Book Chapters
  1. P. Cui, U. Guin, and M. Tehranipoor, "Trillion Sensors Security", in Emerging Topics in Hardware Security, Springer, 2021, [Springer] [BibTeX: cui2021trillion].
  2. U. Guin, and M. Tehranipoor, "Obfuscation and Encryption for Securing Semiconductor Supply Chain", in Hardware Protection through Obfuscation, Springer, 2017, [Springer] [BibTeX: guin2017obfuscation].
Patents
  1. M. Tehranipoor, D. Forte, and U. Guin, "A comprehensive framework for protecting intellectual property in the semiconductor industry", 2017, US2017/037403, WO2017218631 A2. [LINK] [BibTeX: tehranipoor2017comprehensive]
Journal Papers (Accepted)
  1. P. He, U. Guin, and J. Xie, "Novel Low-Complexity Polynomial Multiplication over Hybrid Fields for Efficient Implementation of Binary Ring-LWE Post-Quantum Cryptography," in IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), 2021 [PDF] [BibTeX: he2021novel].
  2. M. Sadi, and U. Guin, "Yield Loss Reduction and Test of AI and Deep Learning Accelerators", IEEE Transactions on Computer-Aided Design of Integrated Circuits (TCAD), 2021 [Link] [BibTeX: sadi2021test].
  3. P. Chowdhury, U. Guin, A. D. Singh, and V. D. Agrawal, "Estimating Operational Age of an Integrated Circuit", in Journal of Electronic Testing: Theory and Applications (JETTA), 2021 [PDF] [BibTeX: chowdhury2021estimating].
  4. A. Jain, Z. Zhou and U. Guin, "TAAL: Tampering Attack on Any Key-based Logic Locked Circuits", in ACM Transactions on Design Automation of Electronic Systems (TODAES), 2021 [PDF] [BibTeX: jain2021taal].
  5. Y. Zhang, A. Jain, P. Cui, Z. Zhou, and U. Guin, "A Novel Topology-Guided Attack and Its Countermeasure Towards Secure Logic Locking", Journal of Cryptographic Engineering, 2020 [LINK] [PDF] [BibTeX: zhang2020novel].
  6. W. Wang, U. Guin, and A. D. Singh, "Aging-Resilient SRAM-based Ture Random Number Generator for Lightweight Devices", Journal of Electronic Testing: Theory and Applications (JETTA), 2020, [LINK] [PDF] [BibTeX: wang2020aging].
  7. J. Mahmod, and U. Guin, "Robust, Low-Cost and Secure Authentication Scheme for IoT Applications", Cryptography, 2020, [LINK] [PDF] [BibTeX: mahmod2020robust].
  8. P. Cui, J. Dixon, U. Guin, and D. DiMase, "A Blockchain-Based Framework for Supply Chain Provenance", IEEE Access, 2019, [LINK] [PDF] [BibTeX: cui2019blockchainProvenance].
  9. P. Cui, U. Guin, A. Skjellum, and D. Umphress, "Blockchain in IoT: Current Trends, Challenges and Future Roadmap", Journal of Hardware and Systems Security (HaSS), 2019, [LINK] [PDF] [BibTeX: cui2019blockchainSurvey].
  10. Y. Zhang and U. Guin, "End-to-End Traceability of ICs in Component Supply Chain for Fighting Against Recycling", Transactions on Information Forensics & Security (TIFS) , 2019, [LINK] [PDF] [BibTeX: zhang2019end].
  11. U. Guin, N. Asadizanjani, and M. Tehranipoor "Standards for Hardware Security", GetMobile: Mobile Computing and Communications , 2019, [LINK] [PDF] [BibTeX: guin2019standards].
  12. B. Cyr, J. Mahmod, and U. Guin, "Low-Cost and Secure Firmware Obfuscation Method for Protecting Electronic Systems from Cloning", IEEE Internet of Things Journal , 2019, [LINK] [PDF] [BibTeX: cyr2019low].
  13. S. Wang, A. Ali, U. Guin, and A. Skjellum, "IoTCP: A Novel Trusted Computing Protocol for IoT", Journal of The Colloquium for Information System Security Education (CISSE), 2018, [LINK] [BibTeX: wang2018iotcp].
  14. U. Guin, Z. Zhou, and A. Singh, “Robust Design-for-Security (DFS) Architecture for Enabling Trust in IC Manufacturing and Test”, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), 2018, [LINK] [PDF] [BibTeX: guin2018robust].
  15. M. Alam, M. Tehranipoor, and U. Guin, “TSensors Vision, Infrastructure and Security Challenges in Trillion Sensor Era: Current Trends and Future Directions”, Journal of Hardware and Systems Security (HaSS), 2017, [LINK] [PDF] [BibTeX: alam2017tsensors].
  16. M. Tehranipoor, U. Guin, and S. Bhunia, “Invasion of the Hardware Snatchers: Cloned Electronics Pollute the Market”, IEEE Spectrum, 2017, [LINK] [BibTeX: tehranipoor2017invasion].
  17. U. Guin, S. Bhunia, D. Forte, and M. Tehranipoor, “SMA: A System-Level Mutual Authentication for Protecting Electronic Hardware and Firmware”, IEEE Transactions on Dependable and Secure Computing (TDSC), 2016, [LINK] [PDF] [BibTeX: guin2016sma].
  18. U. Guin, Q. Shi, D. Forte, and M. Tehranipoor, “FORTIS: A Comprehensive Solution for Establishing Forward Trust for Protecting IPs and ICs”, ACM Transactions on Design Automation of Electronic Systems (TODAES), 2016, [LINK] [PDF] [BibTeX: guin2016fortis].
  19. U. Guin, D. Forte, and M. Tehranipoor, “Design of Accurate Low-Cost On-Chip Structures for protecting Integrated Circuits against Recycling”, IEEE Transactions on VLSI Systems (TVLSI), 2015, [LINK] [PDF] [BibTeX: guin2015design].
  20. U. Guin, K. Huang, D. DiMase, J. M. Carulli Jr., M. Tehranipoor, and Y. Makris, “Counterfeit Integrated Circuits: A Rising Threat in the Global Semiconductor Supply Chain”, Proceedings of the IEEE, 2014, [LINK] [PDF] [BibTeX: guin2014counterfeitProc] (cited in "White House 100-Day Reviews under Executive Order 14017" on "Building Resilient Supply Chains, Revitalizing American Manufacturing, and Fostering Broad-Based Growth").
  21. U. Guin, D. DiMase, and M. Tehranipoor, “Counterfeit Integrated Circuits: Detection, Avoidance, and the Challenges Ahead”, Journal of Electronic Testing: Theory and Applications (JETTA), 2014, [LINK] [PDF] [BibTeX: guin2014counterfeitJETTA] (Most downloaded article in 2014).
  22. U. Guin, D. DiMase, and M. Tehranipoor, “A Comprehensive Framework for Counterfeit Defect Coverage Analysis and Detection Assessment”, Journal of Electronic Testing: Theory and Applications (JETTA), 2014, [LINK] [PDF] [BibTeX: guin2014comprehensive].
Conference Papers
  1. Z. Zhou, U. Guin, P. Li and V. Agrawal, “Defect Characterization and Testing of Skyrmion-Based Logic Circuits,” in VLSI Test Symposium (VTS), 2021, [PDF] [BibTeX: zhou2021defect] (Best Paper Nomination).
  2. S. Kundu, K. Basu, M. Sadi, T. Titirsha, S. Song, A. Das and U. Guin, “Special Session: Reliability Analysis for AI/ML Hardware,” in VLSI Test Symposium (VTS), 2021, [PDF] [BibTeX: kundu2021special].
  3. A. Jain, Z. Zhou, and U. Guin, “Survey of Recent Developments for Hardware Trojan Detection,” in IEEE International Symposium on Circuits & Systems (ISCAS), 2021, [PDF] [BibTeX: jain2021survey].
  4. A. Jain, and U. Guin, “A Novel Tampering Attack on AES Cores with Hardware Trojans,” in ITC-Asia, 2020, [PDF] [BibTeX: jain2020novel].
  5. A. Jain, M. T. Rahman and U. Guin, “ATPG-Guided Fault Injection Attacks on Logic Locking,” in IEEE Physical Assurance and Inspection of Electronics (PAINE), 2020, [LINK] [PDF] [BibTeX: jain2020atpg].
  6. A. Stern, D. Mehta, S. Tajik, U. Guin, F. Farahmandi and M. Tehranipoor, “SPARTA-COTS: A Laser Probing Approach for Sequential Trojan Detection in COTS Integrated Circuits”, in IEEE Physical Assurance and Inspection of Electronics (PAINE), 2020, [LINK] [PDF] [BibTeX: stern2020sparta].
  7. A. Jain, U. Guin, M. T. Rahman, N. Asadizanjani, D. Duvalsaint, and R. D. (Shawn) Blanton, “Special Session: Novel Attacks on Logic-Locking”, in VLSI Test Symposium (VTS), 2020, [LINK] [PDF] [BibTeX: jain2020special].
  8. J. Xie, K. Basu, K. Gaj and U. Guin, “Special Session: The Recent Advance in Hardware Implementation of Post-Quantum Cryptography”, in VLSI Test Symposium (VTS), 2020, [LINK] [PDF] [BibTeX: xie2020special].
  9. W. Wang, U. Guin, and A. Singh, “A Zero-Cost Detection Approach for Recycled ICs using Scan Architecture”, in VLSI Test Symposium (VTS), 2020, [LINK] [PDF] [BibTeX: wang2020zero].
  10. Y. Zhang, P. Cui, Z. Zhou, and U. Guin, “TGA: An Oracle-less and Topology-Guided Attack on Logic Locking”, in Attacks and Solutions in Hardware Security (ASHES), 2019, [LINK] [PDF] [BibTeX: zhang2019tga].
  11. P. Cui and U. Guin, “Countering Botnet of Things using Blockchain-Based Authenticity Framework”, in IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2019, [LINK] [PDF] [BibTeX: cui2019countering].
  12. U. Guin, W. Wang, C. Harper, and A. D. Singh, “Detecting Recycled SoCs by Exploiting Aging Induced Biases in Memory Cells”, in IEEE International Symposium on Hardware Oriented Security and Trust (HOST), 2019, [LINK] [PDF] [BibTeX: guin2019detecting].
  13. J. Mahmod, S. Millican, U. Guin, and V. D. Agrawal, “Special Session: Delay Fault Testing - Present and Future”, in IEEE VLSI Test Symposium (VTS), 2019, [LINK] [PDF] [BibTeX: mahmod2019special].
  14. P. Chowdhury, U. Guin, A. D. Singh and V. D. Agrawal, “Two-Pattern ΔIDDQ Test for Recycled IC Detection”, in International Conference on VLSI Design (VLSID), 2019, [LINK] [PDF] [BibTeX: chowdhury2019two].
  15. U. Guin, P. Cui, and A. Skjellum, “Ensuring Proof-of-Authenticity of IoT Edge Devices using Blockchain Technology”, in IEEE International Conference on Blockchain, 2018, [LINK] [PDF] [BibTeX: guin2018ensuring].
  16. W. Wang, A. D. Singh, U. Guin, and A. Chatterjee, “Exploiting Power Supply Ramp Rate for Calibrating Cell Strength in SRAM PUFs”, in IEEE Latin-American Test Symposium (LATS), 2018, [LINK] [PDF] [BibTeX: wang2018exploiting].
  17. M. Alam, S. Chowdhury, M. Tehranipoor, and U. Guin, “Robust, Low-Cost, and Accurate Detection of Recycled ICs using Digital Signatures”, in IEEE International Symposium on Hardware Oriented Security and Trust (HOST), 2018, [LINK] [PDF] [BibTeX: alam2018robust].
  18. Z. Zhou, U. Guin, and V. D. Agrawal, “Modeling and Test Generation for Combinational Hardware Trojans”, in IEEE VLSI Test Symposium (VTS), 2018, [LINK] [PDF] [BibTeX: zhou2018modeling].
  19. U. Guin, A. D. Singh, M. Alam, J. Canedo, and A. Skjellum, “A Secure Low-Cost Edge Device Authentication Scheme for the Internet of Things”, in International Conference on VLSI Design, 2018, [LINK] [PDF] [BibTeX: guin2018secure].
  20. U. Guin, “Efficient Strategies for Detection and Avoidance of Counterfeit ICs”, IEEE North Atlantic Test Workshop (NATW), 2017, [PDF] [BibTeX: guinefficient].
  21. U. Guin, Z. Zhou, and A. D. Singh, “A Novel Design-for-Security (DFS) Architecture to Prevent Unauthorized IC Overproduction”, IEEE VLSI Test Symposium (VTS), 2017, [LINK] [BibTeX: guin2017novel].
  22. B. Shakya, U. Guin, M. Tehranipoor and D. Forte, “Performance Optimization for On-Chip Sensors to Detect Recycled ICs”, IEEE International Conference on Computer Design (ICCD), 2015, [LINK] [BibTeX: shakya2015performance].
  23. U. Guin, X. Zhang, D. Forte, and M. Tehranipoor, “Low-Cost On-Chip Structures for Combating Die and IC Recycling”, Design Automation Conference (DAC), 2014, [LINK] [BibTeX: guin2014low].
  24. U. Guin, D. Forte, D. DiMase, and M. Tehranipoor, “Counterfeit IC Detection: Test Method Selection Considering Test Time, Cost, and Tiel Level Risk”, GOMACTech, 2014, [PDF] [BibTeX: guin2014icdetect].
  25. U. Guin, D. Forte, and M. Tehranipoor, “Low-cost On-Chip Structures for Combating Die and IC Recycling”, GOMACTech, 2014. [PDF] [BibTeX: guin2014cost].
  26. U. Guin, D. Forte, and M. Tehranipoor, “Anti-Counterfeit Techniques: From Design to Resign”, IEEE Microprocessor Test Verification (MTV), 2013, [LINK] [BibTeX: guin2013anti].
  27. U. Guin and M. Tehranipoor, “CDIR: Low-Cost Combating Die/IC Recycling Structures”, DMSMS, 2013, (Extended Abstract) [LINK] [BibTeX: guin2013cdir].
  28. U. Guin, T. Chakraborty, and M. Tehranipoor, “Functional Fmax Test-Time Reduction using Novel DFTs for Circuit Initialization”, IEEE Int. Conference on Computer Design (ICCD), 2013, [LINK] [BibTeX: guin2013functional].
  29. U. Guin, T. Chakraborty, and M. Tehranipoor, “Novel DFTs for Circuit Initialization to Reduce Functional Fmax Test Time”, IEEE North Atlantic Test Workshop (NATW), 2013, [PDF] [BibTeX: guin2013novel].
  30. U. Guin and M. Tehranipoor, “On Selection of Counterfeit IC Detection Methods”, IEEE North Atlantic Test Workshop (NATW), 2013, [PDF] [BibTeX: guin2013selection], (Received Best Paper Award).
  31. U. Guin, and M. Tehranipoor, “Counterfeit Detection Technology Assessment”, GOMACTech, 2013, [PDF] [BibTeX: guin2013asses].
  32. N. Murphy, U. Guin, and M. Tehranipoor, “Counterfeit Detection Technology Assessment”, DMSMS & Standardization, 2012, [BibTeX: murphy2012asses].
  33. U. Guin and C. -H. Chiang, “Design for Bit Error Rate Estimation of High Speed Serial Links”, IEEE VLSI Test Symposium (VTS), 2011, [BibTeX: guin2011design].
Posters
  1. Y. Zhang, P. Cui, Z. Zhou, and U. Guin, “SAL: Function Search Attack on Logic Locked Circuits”, International Test Conference, 2019. [PDF].
Technical Reports
  1. U. Guin, M. Tehranipoor, D. DiMase, and M. Megrdician, “Counterfeit IC Detection and Challenges Ahead”, ACM SIGDA, 2013, [PDF] [BibTeX: guin2013counterfeit].
Thesis
  1. U. Guin, “Establishment of trust and integrity in modern supply chain from design to resign”, PhD Thesis, University of Connecticut, CT, 2016, [LINK].
  2. U. Guin, “Design for Bit Error Rate Estimation of High Speed Serial Links”, Masters Thesis, Temple University, PA, 2010.