ELEC 5200-001/6200-001 Computer Architecture and Design
Fall 2010, MWF 11AM, Broun 306
Course Syllabus,
Grades
Statistics
Instructor: Vishwani D. Agrawal, James J. Danaher Professor of ECE
Teaching Assistant: Manish Kulkarni, 334-332-0556, B359,
consulting hours: MWF 10:00-11:00AM.
EXAM SCHEDULE:
Test 1, Wednesday, 10/6/10, 11:00-11:50AM, Broun 306, use of books, notes, etc., permitted,
statistic.
Test 2, Wednesday, 11/3/10, 11:00-11:50AM, Broun 306, use of books, notes, etc., permitted,
statistic.
Final Exam, Wednesday, Dec 8, 2010, 12:00-2:30PM, Broun 306, use of books, notes, etc., permitted,
statistic
PROJECT:
Fall 2010 Project Assignment, Monday, 10/4/10
Part 1 ISA, report due Wednesday, 10/13/10
Part 2 Datapath, report due Wednesday, 10/20/10
Part 3 Datapath Verification, report due Monday, 11/1/10
Part 4 Control Unit, report due Monday, 11/15/10
Part 5 Hardware Implementation and a working processor demo, report due Monday, 11/29/10
INSTRUCTIONS FOR DEMO:
1. Briefly describe what is implemented, what program you will run and what result is expected.
2. Run the program pointing to the functions of the buttons you press. Let the viewer examine the result.
3. Offer to make a change to some parameter to a viewer selected value and rerun the demo.
4. Total duration of demo: FIVE MINUTES.
SCHEDULE FOR IN-CLASS PRESENTATION (15 minutes each project):
Nov 19:
Uppu,
Venkataramani,
White
Nov 29:
{Bradley, Sheshadri},
{Chen, Gao},
Harley
Dec 1:
Beck,
Brown,
Richard
Dec 3:
{Alagappan, Shinde},
Dacunha,
Owahid,
Tacey
Project feedback from Fall 2010 students:
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Project feedback from Spring 2010 students:
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Project feedback from Fall 2009 students:
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Project feedback from Spring 2009 students:
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Project feedback from Fall 2008 students:
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Project feedback from Spring 2008 students:
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Project feedback from Fall 2007 students:
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VHDL references and relevant files for Project:
Guest Lecture by V. Nelson: Modeling and Simulating ASIC Designs with VHDL, 8/20/10
VHDL Review (Lecture from Fall 2009)
Modeling for Synthesis (Lecture from Fall 2009)
Overview of VHDL by Prof. Stroud
References on VHDL by Prof. Stroud
Lectures from Prof. Nelson's CAD course
Altera Quartus II and DE2 manual
Leonardo Spectrum for Altera HDL Synthesis Manual
Altera MegaWizard Plug-In Manager Manual
Run_time_content_editable_memory_tutorial.pdf
VHDL Files: hexto7seg.vhd,
regfile.vhd
HOMEWORK:
Homework 1, assigned 8/30/10, due 8/6/10,
solution
Homework 2, assigned 9/6/10, due 9/13/10,
solution
Homework 3: Design of 16-bit ALU and its implementation in FPGA, assigned 9/13/10, due 9/27/10
Files relevant to Homework 3:
hw3.zip,
Modelsim_Tutorial,
Run_time_content_editable_memory_tutorial,
DE2_pin_assignments.xls,
Altera Quartus II and DE2 manual
Homework 4, assigned 9/27/10, due 10/4/10,
solution
Homework 5, assigned 10/4/10, due 10/11/10,
solution
Homework 6, assigned 10/25/10, due 11/1/10,
solution
Homework 7, assigned 11/1/10, due 11/8/10,
solution
Homework 8, assigned 11/15/10, due 11/29/10,
solution
LECTURES: See webpages of most recent years.
PREVIOUS OFFERINGS BY PROF. V. AGRAWAL:
Spring 2010
Fall 2009
Spring 2009
Fall 2008
Spring 2008
Fall 2007
Spring 2007
Fall 2006
Fall 2005
Fall 2004