ELEC 5200-001/6200-001 Computer Architecture and Design
Spring 2008, MWF 11AM, Broun 306
Course Syllabus Grades Statistics
Instructor: Vishwani D. Agrawal, James J. Danaher Professor of ECE

EXAM SCHEDULE:
Test 1, REVISED DATE, Wednesday, 3/5/08, 11:00-11:50AM, Broun 306, statistic.
Test 2, Friday, 4/18/08, 11:00-11:50AM, Broun 306, statistic.
Final Exam, Friday, 5/2/08, 9:00AM-11:30AM, Broun 306, use of books, notes, etc., permitted. To prepare, review material on pipeline, performance, arithmetic and cache, statistic

PROJECT:
Must read Part 5 reports from Fall 2007 students before starting this project: 1 2 3 4 5 6 7 8 9 10 11 12
Assignment, Presentation, Monday, 3/10/08
Part 1 - ISA, report due Monday, 3/24/08
Part 2 - Datapath, report due Monday, 3/31/08
Part 3 - Datapath Verification, report due Monday, 4/7/08
Part 4 - Control Unit, report due Monday, 4/14/08
Part 5 - FPGA Implementation, demo and report due Monday, 4/21/08
VHDL References:
Slides from Prof. Nelson's site: Synthesis with VHDL and Leonardo.
Lectures from Prof. Nelson's CAD course.
Altera Quartus II and DE2 Manual.
Leonardo Spectrum for Altera HDL Synthesis Manual
Useful files:
qsim_logic.vhd. Compile and add "qsim_logic.vhd" to your current working directory. This will enable the 'to_interger' and 'to_stdlogicvector' functions used in the other files.
regfile.vhd is the code for a register file.
trans.vhd contains the code for a bidirectional bus interface.
Files for Part 4:
test.c is a test program in C. You may choose a different program for demo in Part 5.
Files for Part 5:
Altera MegaWizard Plug-In Manager Manual.
Altera DE2 Pin Assignments.
RAM_init.mif, Memory initialization file.
Part 5 reports from Spring 2008 students: 1 2 3 4 5 6 7 8 9

CLASS PRESENTATIONS (A student must attend at least 2 presentations for a satisfactory grade):
4/25/08 Menon: URISC - The Ultimate RISC Archtecture slides
4/28/08 Andrews: Single-Chip Multi-Processors (CMP) slides
4/28/08 Kulkarni: CISC - Complex Instruction Set Computers slides

HOMEWORKS:
Homework 1: VHDL, controller.vhd, assigned 1/9/08, due 1/23/08.
Homework 2, assigned 1/30/08, due 2/8/08.
Homework 3, assigned 2/11/08, due 2/18/08.
Homework 4, assigned 2/20/08, due 2/27/08.
Homework 5, assigned 3/10/08, due 3/24/08.
Homework 6, assigned 3/26/08, due 4/2/08.
Homework 7, assigned 4/21/07, due 4/25/07.

LECTURES: See webpages of most recent years.

PREVIOUS OFFERINGS BY PROF. V. AGRAWAL:
Fall 2007 Spring 2007 Fall 2006 Fall 2005 Fall 2004