ELEC 5200-001/6200-001 Computer Architecture and Design
Fall 2005
Course Syllabus, Grading Sheet Grade Statistics

EXAMINATIONS:

Test I, 10/07/05 (Friday), 8:00AM - 8:50AM, Broun 306, Solution, Statistics
This test includes Chapters 1, 2 and 3. Specifically, computer history (only what is in class notes), basic understanding and use of instruction set, register saving and restoring, two's complement arithmetic. Use of text-book, class presentations, notes, past homeworks and solutions is permitted.

Test II, 11/09/05 (Wednesday), 8:00AM - 8:50AM, Broun 306, Solution, Statistics
This test includes Chapters 4 and 5, performance, datapath and control. Use of text-book, class presentations, notes, past homeworks and solutions is permitted.

Final Exam, 12/09/05 (Friday), 11:00AM - 1:30PM, Broun 306, Question paper (2 pages), Solution (5 pages), Statistics
Text book, notes and course website material permitted. While a student is responsible for the entire syllabus, the following hints might help the preparation. The exam will contain five multi-part questions (all to be attempted), each carrying 5 points. Specific topics of the questions are:
1. Cache memories
2. Pipeline hazards
3. Definitions and basic ideas in advanved architectures (superscalar, VLIW, etc.)

LECTURES:

Note: To print the folowing powerpoint slides, on the "Print" panel, select "Handouts" from the "Print what:" menu and "Pure black and white" from the "Color/grayscale:" menu.

Lecture 1, 08/17/05 Introduction
Lecture 2 (Revised 08/21/05), 08/19/05 and 08/22/05 History of Computers (Chapter 1)
Lecture 3, 08/24/05 and 08/26/05 Instruction Set Architecture (Chapter 2)
Lecture 4, 08/29/05 through 09/07/05 VHDL by Prof. Vic Nelson
Additional material on VHDL can be seen at ELEC 4200 site of Prof. C. E. Stroud
Lecture 5, 9/09/05 Preparing a Program to Run (Chapter 2)
Lecture 6, 9/12/05 Saving and Restoring Registers (Chapter 2)
Lecture 7, 9/14/05 through 9/23/05 Computer Arithmetic (Chapter 3)
Lecture 8, 9/26-30/05 Symbols and Floating Point Numbers (Chapters 2 and 3)
Lecture 9, 10/3-17/05 Datapath and Control (Chapter 5)
Lecture 10, 10/19-21/05 Control Unit: Hard-Wired and Microcoded (Chapter 5)
Lecture 11, 10/26-28/05 Performance of a Computer (Chapter 4)
Lecture 12, 10/31-11/07/05 Pipelining (Chapter 6)
Lecture 13, 11/16-18/05 Pipelined Control and Performance (Chapter 6)
Lecture 14, 11/28/05 - 12/5/05 Memory Organization (Chapter 7)
Lecture 15, 12/7/05 Conclusion

COMPUTER DESIGN PROJECT, assigned 9/28/05, due dates: Part 1-10/12/05, Part 2-10/26/05, Part 3-11/16/05, Part 4-12/02/05 (Extended, FINAL deadline)
The following VHDL files can be downloaded:
qsim_logic.vhd. Compile and add "qsim_logic.vhd" to your current working directory. This will enable the 'to_interger' and 'to_stdlogicvector' functions used in the other files.
regfile.vhd is the code for a register file.
trans.vhd contains the code for a transceiver (bus interface).
Additional files for Part IV:
memory16.vhd is VHDL description of memory.
test.c is the C-code to be hand-compiled into assembly code and then into machine code.
program is an example binary machine code that is loaded by the memory16.vhd into the memory.
NOTE: This "program" is provided only as an example. The student should create own program from the provided C-code. This file should not have ".txt" or any other extension.

HOMEWORKS:

Help and Consultation:
VHDL and Project: Alok Doshi, doshias@auburn.edu, Broun 309, x41864, available MWF 9:30-10:30AM
Other homeworks: Fei Hu, hufei01@auburn.edu, Broun 363, x41861

Homework 1, Problems 1.29 through 1.45, and 1.56, assigned 08/19/05, due 09/02/05, Solution
Homework 2, Problems 2.30 and 2.31, assigned 08/26/05, due 09/09/05, Solution
Homework 3, assigned 09/02/05, due 09/16/05
Homework 4, assigned 09/09/05, due 09/23/05
Homework 5, Problems 2.37, 2.38 and 3.7, assigned 09/16/05, due 09/30/05, Solution
Homework 6, assigned 9/23/05, due 10/07/05, Solution
      Note: Use 8-bit two's complement representation for these problems.
      Problem 1: Write decimal integers, 77, -77, 15, -15, in 8-bit two's complement form.
      Problem 2: Evaluate 77(ten) + 77(ten).
      Problem 3: Evaluate 77(ten) - 15(ten).
      Problem 4: Evaluate the product -77 x 15 using the Booth multiplication algorithm.
      Problem 5: Perform the division 77/15 using the non-restoring binary division algorithm.
Homework 7, Problem 3.43, assigned 9/30/05, due 10/14/05, Solution
Homework 8, Problems 5.8 and 5.28, assigned 10/14/05, due 10/28/05, Solution
Homework 9, Problems 5.35 and 5.51, assigned 10/21/05, due 11/4/05, Solution
Homework 10, Problems 4.7, 4.8 and 4.11, assigned 10/28/05, due 11/11/05, Solution
Homework 11, Problems 6.3 and 6.21, assigned 11/4/05, due 11/18/05, Solution

TERM PAPERS AND CLASS PRESENTATIONS:

Important: Unsatisfactory completion of this part of the course can result in up to one letter grade reduction. "Satisfactory" for 6200 means talk preparation and presentation. For 5200, "satisfactory" means attendance in at least four out of six presentations.
Instructions: There will be no term paper required. Each class presentation will have 20-25 minute duration and will use up to 16 (max) powerpoint slides including the title and conclusion slides. The talk must define terms and present main concepts in the simplest possible way. Relevant formulas should be given and the use of simple diagrams and graphs is encouraged. Most relevant references should be included. Questions and discussion during presentation are encouraged. Slides will be placed at the course website, preferably before the talk. Topic assignments:
Anbumony: Superscalars, 10/24/05, slides
Chen: Multi-processor SOC, 11/14/05, slides
Jain: Virtual memory, 11/14/05, slides
Ramamurthy: CISC, 11/11/05, slides
Sheth: Performance and power benchmarks, 10/24/05, slides
Wang: VLIW, 11/11/05, slides