ELEC 5200-001/6200-001 Computer Architecture and Design
Fall 2004
Course Syllabus, Grading Sheet Grade Statistics

Final Exam, 12/13/04 (Monday), 11:00AM - 1:30PM, Broun 306, text book, notes and course website material permitted. While a student is responsible for the entire syllabus, the following hints might help the preparation. The exam will contain five multi-part questions (all to be attempted), each carrying 5 points. Specific topics of the questions are:
1. Computer arithmetic - two's complement numbers, addition, Booth multiplication.
2. Single-cycle datapath.
3. Pipelining - MIPS (instruction set) datapath, data hazard, control.
4. Performance - CPU time, MIPS (million instructions per second) rating, advanced architectures (e.g., ILP, superscalar, VLIW).
5. Cache - direct-mapped and associative caches, consistency.

Lecture 1, 08/18/04 Introduction
Lecture 2 (updated), 08/20/04 and 08/23/04 History of Computers
Lecture 3 (3rd revision, corrected 09/03/04), 08/25/04 through 09/03/04 VHDL by Vic Nelson
Additional material on VHDL can be seen at ELEC 4200 site of Prof. C. E. Stroud
Lecture 4 (2nd revision 09/20/04), 09/08/04 through 09/22/04 Theory of Computing and Instruction Set
Lecture 5, 9/22/04 Preparing a Program to Run
Lecture 6, 9/27/04 Saving and Restoring Registers
Lecture 7 (updated 10/8/04), 9/29/04 through 10/8/04 Computer Arithmetic
Lecture 8 (updated 10/13/04), 10/11/04 and 10/13/04 Symbol Representation and Floating Point Arithmetic
Lecture 9 (updated 10/29/04), 10/15-29/04 Datapath and Control
Lecture 10 (updated 11/2/04), 11/1-3/04 Control Unit: Hard-Wired and Microcoded
Lecture 11 (updated 11/7/04), 11/5-8/04 Performance of a Computer
Lecture 12 (updated 11/14/04), 11/10-15/04 Pipelining
Lecture 13 (updated 11/19/04), 11/17-19/04 Pipelined Control
Lecture 14 (updated 12/6/04), 11/29/04 - 12/6/04 Memory Organization
Lecture 15, 12/8/04 Conclusion


COMPUTER DESIGN PROJECT, assigned 9/29/04, Part IV due 12/8/04 (FINAL DEADLINE)
The following VHDL files can be downloaded:
qsim_logic.vhd. Compile and add "qsim_logic.vhd" to your current working directory. This will enable the 'to_interger' and 'to_stdlogicvector' functions used in the other files.
regfile.vhd is the code for a register file.
trans.vhd contains the code for a transceiver (bus interface).
Additional files for Part IV:
memory16.vhd is VHDL description of memory.
test.c is the C-code to be hand-compiled into assembly code and then into machine code.
program is an example binary machine code that is loaded by the memory16.vhd into the memory.
NOTE: This "program" is provided only as an example. The student should create own program from the provided C-code.


Homework 1, assigned 08/20/04, due 09/20/04, Solution
Problems 1.52 and 1.54 in the third edition of text-book
1.52: In this exercise, you will evaluate the performance difference between two CPU architectures, CISC (Complex Instruction Set Computing) and RISC (Reduced Instruction Set Computing). Generally speaking, CISC CPUs have more complex instructions than RISC CPUs and therefore need fewer instructions to perform the same tasks. However, typically one CISC instruction, since it is more complex, takes more time to complete than a RISC instruction. Assume that a certain task needs P CISC instructions 2P RISC instructions, and that one CISC instruction takes 8T ns to complete, and one RISC instruction takes 2T ns. Under this assumption, which one has the better performance?
1.54: Sometimes software optimization can dramatically improve the performance of a computer system. Assume that a CPU can perform a multiplication operation in 10 ns, and a subtraction operation in 1 ns. How long will it take for the CPU to calculate the result of d = a x b - a x c? Could you optimize the equation so that it will take less time?

Homework 2, assigned 08/27/04, due 09/03/04, Solution

Homework 3, assigned 09/03/04, due 09/13/04, Solution

Homework 4, assigned 09/13/04, due 09/24/04, Solution
Problems 2.38 and 2.47 from Third Edition (or Problems 3.11 and 3.12 from Second Edition)

Homework 5, assigned 10/1/04, due 10/8/04, Solution
Problems 3.1 through 3.6 from Third Edition (or Problems 4.1 through 4.6 from Second Edition))
Note: The data in the two editions differ. Please indicate on your answers which edition you have used.

Homework 6, assigned 10/15/04, due 10/22/04, Solution
Problem 1: Evaluate the product -86 x 31 using the Booth multiplication algorithm.
Problem 2: Perform the division 86/31 using the non-restoring binary division algorithm.

Homework 7, assigned 11/1/04, due 11/8/04, Solution
Problem 5.2 Describe the effect that a single stuck-at-0 fault (i.e., regardless of what it should be, the signal is always 0) would have for the signals shown below in the single-cycle datapath in Figure 5.17 on page 307 (Figure 5.19 on page 360 for Second Edition). Which instructions, if any, will not work correctly? Explain why. Consider the following faults separately: (a) RegWrite = 0; (b) ALUOp0 = 0; (c) ALUOp1 = 0; (d) Branch = 0; (e) MemRead = 0; (f) MemWrite = 0.

Homework 8, assigned 11/8/04, due 11/15/04, Solution
Problems 4.14 and 5.36 (both from Third Edition)
If you use the Second Edition, please obtain the relevant pages from a colleague or from Mr. Fei Hu.

Homework 9, assigned 11/15/04, due 11/29/04, Solution
Problems 6.4 and 6.22 (Third Edition)
or Problems 6.4 and 6.15 (Second Edition)

Homework 10, assigned 11/29/04, due 12/6/04, Solution
Problems 7.9 and 7.12 (Third Edition)


EXAMS

Test 1 solution, Result statistics
Test 2 solution, Result statistics
Test 3 solution, Result statistics
Final Exam solution, Result statistics