Spring 2013, MWF 2PM, Broun 113

Course Syllabus, Grade Sheet

Instructor: Vishwani D. Agrawal, James J. Danaher Professor of ECE

CLASS TEST: Friday, Apr 5, 2013, Broun 113, 2:00PM - 2:50PM, books, notes, computer, etc., permitted, statistic

FINAL EXAM: Monday, Apr 29, 2013, Broun 113, 4:00PM - 6:30PM, books, notes, computer, etc., permitted, statistic

ANNOUNCEMENTS:

1/10/13 Auburn Co-Op Employment Opportunities

HOMEWORK:

Homework 1, assigned 1/11/13 due 1/23/13

. . . Computer Setup for EDA Tools by M. Dharan

. . . HSPICE User Guide: Simulation and Analysis

. . . add.vhd

. . . Review of VHDL by N. Yogi

Homework 2, assigned 2/13/13, due 2/20/13, website for possible download of an LP solver

Homework 3, assigned 3/18/13, due 3/29/13

Homework 4, assigned 4/15/13, due 4/22/13

PROJECT: Assignment 2/13/13, final report due 4/15/13

Report, 4-6 pages in two-column publishable paper format (10 points)

Slides, 5 max including title (5 points)

Class presentation, 5 minutes (10 points)

LECTURES:

Guest Lectures: Tools for Power Analysis by Murali Dharan, 1/9/13, 1/11/13

Lecture 1: Introduction to Low Power Design, 1/14/13 . . .

Lecture 2: Power Dissipation of CMOS Circuits, 1/18/13 . . .

Lecture 3: Gate-Level Power Analysis, 1/28/13 . . .

Lecture 4: Linear Programming, 2/6/13 . . .

LP Solvers:

. . . PHPSimplex Online Solver

. . . LINDO Download

Lecture 5: Gate-Level Power Optimization, 2/15/13 . . .

Lecture 6: Test Power, 2/25/13 . . .

Lecture 7: Energy Source Design, 3/8/13 . . .

Lecture 8: Power Aware Microprocessors, 3/20/13 . . .

Lecture 9: Memory and Multicore Design, 3/27/13 . . .

Lecture 10: Adiabatic Logic, 4/3/13 . . .

Lecture 11: Pseudo-nMOS, Dynamic CMOS and Domino CMOS Logic, 4/12/13 . . .

Lecture 12: Pass Transistor Logic: A Low Power Logic Family, 4/15/13 . . .

READING ASSIGNMENTS:

Power Constrained Test:

3/4/13: Y. Bonhomme, et al., "Power Driven Chaining of Flip-Flops in Scan Architectures,” Proc. International Test Conf., 2002, pp. 796–803.

3/6/13: V. Sheshadri, et al., "Optimal Power-Constrained SoC Test Schedules With Customizable Clock Rates,” Proc. 25th IEEE International System-on-Chip Conf., 2002, pp. 271–276.

3/6/13: V. Sheshadri, et al., "Optimum Test Schedule for SoC with Specified Clock Frequencies and Supply Voltages,” Proc. 26th International Conf. on VLSI Design, 2002, pp. 267–272.

3/6/13: P. Venkataramani and V. D. Agrawal, "Reducing Test Time of Power Constrained Test by Optimal Selection of Supply Voltage,” Proc. 26th International Conf. on VLSI Design, 2002, pp. 273–278.

Managing Power Source:

3/8/13: R. W. Erikson, "DC-DC Power Converters," Wiley Encyclopedia of Electrical and Electronics Engineering.

3/8/13: M. Chen and G. A. Rincon-Mora, "Accurate Electrical Battery Model . . . ," IEEE Trans. Energy Conversion, vol. 21, no. 2, pp. 504-511, June 2006.

3/8/13: M. Kulkarni and V. D. Agrawal, "Energy Source Lifetime Optimization . . . ," Proc. SSST, Auburn, March 14-16, 2011, pp. 75-80.

Power Management of Processors:

3/20/13: T. Sakurai, "Alpha Power-Law Model," IEEE Solid-State Circuits Society Newsletter, vol. 9, no. 4, pp. 4-5, Oct. 2004.

3/20/13: A. Shinde and V. D. Agrawal, "Managing Performance and Efficiency of a Processor," Proc. 45th SSST, March 11, 2013.

Multicore Power:

3/27/13: M. D. Hill and M. R. Marty, "Amdahl's Law in Multicore Era," Computer, vol. 41, no. 7, pp. 33-38, July 2008.

3/27/13: D. H. Woo and H.-H. S. Lee, "Extending Amdahl's Law for Energy-Efficient Computing in the Many-Core Era," Computer, vol. 41, no. 12, pp. 24-31, December 2008.

4/3/13: M. Bohr, "A 30 Year Retrospective on Dennard's MOSFET Scaling Paper".

4/3/13: 1974 paper by Dennard et al.

4/10/13: Read about recycling of clock energy in "Good Timing," IEEE Spectrum, vol. 49, no. 7, pp. 11-12, July 2012.

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