Fall 2007, TuTh 2PM, Broun 306

Course Syllabus, Grades

EXAM SCHEDULE: December 11, 2007, Broun 306, 2:00PM - 4:30PM

Take-Home Exam, assigned Dec 10, 2007, due Dec 11, 2007, until midnight.

HOMEWORKS:

Homework 1, assigned 10/9/07, due 10/16/07.

Homework 2, assigned 10/23/07, due 11/11/07.

Homework 3, assigned 11/12/07, due 11/16/07.

Homework 4, assigned 11/21/07, due 11/29/07.

PROJECTS, assigned 11/6/07, report due 12/6/07

Project report will be in the form of ~10 slides used for class presentation:

1. Bandi, Chaitanya (12/4/07): Ring oscillator frequency and power versus voltage

2. Erickson, Christopher (12/6/07): Design of benchmark circuit (s5378) for reduced scan mode activity

3. Govindasamy, Kannan (12/6/07): Reduced power shift register with multiphase clocks

4. Jiang, Wei (11/29/07): Low power 32-bit bus with inversion encoding, References: [1] [2]

5. Langford, Matthew Luther: Three bit binary counters with decimal and Gray encodings

6. Luo, Lan (12/4/07): 32-bit parallel load register with clock gating, References: [1] [2] [3]

7. Menon, Sreekumar Narayanan (11/29/07): Normal speed 32-bit adder with reduced supply and parallelism

8. Shukoor, Mohammed Ashfaq (11/29/07): 32-bit adder for low voltage operation with level converters, References: [1] [2]

9. Wei, Xiaoyun (Audit): Reduced power shift register with clock gating

10. Xu, Ziyan (12/4/07): Very low voltage operation of a 16-bit counter

11. Yao, Jia (12/4/07): Characterization of a CMOS cell library for low-voltage operation

12. Zhang, Tong (12/6/07): Low power analog or RF amplifier

LECTURES:

Lecture 1: Introduction, 8/16/07

Lecture 2: Dynamic and Static Power in CMOS, 8/21/07

Lecture 3: Logic-Level Power Estimation, 8/28/07

Lecture 4: Power Analysis: High-Level, 9/6/07

Lecture 5: Low Voltage Low-Power Devices, 9/11/07

Lecture 6: Dynamic Power: Device Sizing, 9/18/07

Lecture 7: Gate-Level Power Optimization, 9/20/07

Lecture 8: Linear Programming - A Mathematical Optimization Technique, 10/2/07

Lecture 9: Test Power, 10/9/07

Lecture 10: Memory and Multicore Design, 10/9/07

Lecture 11: Adiabatic Logic, 11/1/07

Lecture 12: Pass Transistor Logic: A Low Power Logic Family, 11/8/07

Lecture 13: Pseudo-nMOS, Dynamic CMOS and Domino CMOS Logic, 11/15/07

Lecture 14: Power Aware Microprocessors, 11/27/07

READING ASSIGNMENTS:

R. I. Bahar, D. Hammerstrom, J. Harlow, W. H. Joyner Jr., C. Lau, D. Marculescu, A. Orailoglu and M. Pedram,

Architectures for Silicon Nanoelectronics and Beyond, Computer, vol. 40, no. 1, pp. 25-33, January 2007.

Following articles from Communications of the ACM, vol. 50, no. 9, September 2007:

. . . T. Munakata, Beyond Silicon: New Computing Paradigms, pp. 30-34.

. . . W. Robinett, G. S. Snider, P. J. Kuekes and S. Williams, Computing with a Trillion Crummy Components, pp. 35-39.

. . . J. Kong, Computation with Carbon Nanotube Devices, pp. 40-42.

. . . R. Stadler, Molecular, Chemical and Organic Computing, pp. 43-45.

. . . J. H. Reif and T. H. Labean, Autonomous Programmable Biomolecular Devices using Self-Assembled DNA Nanostructures, pp. 46-53.

. . . D. Bacon and D. Leung, Toward a World with Quantum Computers, pp. 55-59.

. . . H. Abdeldayem and D. A. Frazier, Optical Computing: Need and Challenge, pp. 60-62.

. . . D. W. M. Marr and T. Munakata, Micro/Nanofluidic Computing, pp. 64-68.

. . . M. Aono, M. Hara and K. Aihara, Amoeba-Based Neurocomputing with Chaotic Dynamics, pp. 69-72.

M. T. Bohr, R. S. Chau, T. Ghani and K. Mistry, "The High-k Solution," IEEE Spectrum, vol. 44, no. 10, pp. 29-35, October 2007

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