library ieee; use ieee.std_logic_1164.all; library work; use work.qsim_logic.all; entity regfile is port( clock : in bit; regwr : in bit; wrreg : in bit_vector(3 downto 0); rr1 : in bit_vector(3 downto 0); rr2 : in bit_vector(3 downto 0); wrdata : in bit_vector(15 downto 0); rd1 : out bit_vector(15 downto 0); rd2 : out bit_vector(15 downto 0); inr: in bit_vector(3 downto 0); outvalue: out bit_vector(15 downto 0) ); end regfile; architecture rtl of regfile is type regs is array(0 to 15) of bit_vector(15 downto 0); signal reg : regs; begin process(clock) begin if clock'event and clock = '1' then if regwr = '1' then if (wrreg = "0000") then reg(to_integer('0' & wrreg)) <= "0000000000000000"; -- Register 0 hardwired to zero. else reg(to_integer('0' & wrreg)) <= wrdata; end if; end if; end if; end process; rd1 <= reg(to_integer('0' & rr1)); rd2 <= reg(to_integer('0' & rr2)); process (inr,reg) begin case inr is when "0000" => outvalue<=reg(0);-- used to display the contents of the registers on FPGA in the final part. when "0001" => outvalue<=reg(1); when "0010" => outvalue<=reg(2); when "0011" => outvalue<=reg(3); when "0100" => outvalue<=reg(4); when "0101" => outvalue<=reg(5); when "0110" => outvalue<=reg(6); when "0111" => outvalue<=reg(7); when "1000" => outvalue<=reg(8); when "1001" => outvalue<=reg(9); when "1010" => outvalue<=reg(10); when "1011" => outvalue<=reg(11); when "1100" => outvalue<=reg(12); when "1101" => outvalue<=reg(13); when "1110" => outvalue<=reg(14); when "1111" => outvalue<=reg(15); when others => outvalue<="0000000000000000"; end case; end process; end rtl;