-- component: CONTROLLER --------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.all;

entity controller is				-- FSM model
port(	ctrl_clk:	in std_logic;
	ctrl_rst:	in std_logic;
	sig_in:		in std_logic;
	data_lo_ld:	out std_logic;
	data_hi_ld:	out std_logic;
	data_out_ld:	out std_logic;
	sig_out:	out std_logic;
	count_loops: out std_logic_vector(3 downto 0)
);
end controller;

architecture fsm of controller is

type stateType is( ST0,ST1,ST2,ST3,ST4,ST5,ST6,ST7,ST1a,ST4a,ST7a );
signal currentState, nextState: stateType;				   

begin

-- Process 'p1' models the sequential logic which stores the current state
-- The current state is reset to ST0 on application of async. reset signal
p1: process(ctrl_clk, ctrl_rst)
begin
   if (ctrl_rst='1') then          
	   currentState <= ST0;       -- when reset is asserted reset state to ST0
   else                             
	   currentState <= nextState;	-- when clock toggles load next state
   end if;  
end process;

-- Process 'p2' counts the no. of times the state ST7a was traversed
-- The count is reset to 0 when it goes beyond 9
p2: process(currentState)
variable count: integer;
begin
   if (currentState = ST7a) then
	   count:=count+1;
	   if (count>9) then
	       count:=0;
	   end if;
   end if;  
   count_loops<=std_logic_vector(to_unsigned(count, 4));
end process;
	
-- Process 'p3' models the combinational logic which determines 
-- the next state from the current state and the input signal 'sig_in'	
p3: process(currentState,sig_in)
begin							  
    case currentState is
	when ST0 =>	data_lo_ld <= '0';	-- WaitFirst4	
			data_hi_ld <= '0';
			data_out_ld <= '0';
			sig_out	<= '0';
			if (sig_in='1') then	   		    
			    nextState <= ST1; -- goto state ST1
			end if;               -- else remain in state ST0   

 	when ST1 =>	data_lo_ld <= '1';	-- RecFirst4Start
  			data_hi_ld <= '0';
			data_out_ld <= '0';
			sig_out	<= '0';
			nextState <= ST1a;      -- goto state ST1a

	when ST1a =>	data_lo_ld <= '1';	-- RecFirst4Start
  			data_hi_ld <= '0';
			data_out_ld <= '0';
			sig_out	<= '0';
			nextState <= ST2;      -- goto state ST2

	when ST2 =>	data_lo_ld <= '0';	-- RecFirst4End
			data_hi_ld <= '0';
			data_out_ld <= '0';
			sig_out	<= '0';
			if (sig_in='0') then
			    nextState <= ST3;   -- goto state ST3    
			end if;                 -- else remain in state ST2

	when ST3 =>	data_lo_ld <= '0';	-- WaitSecond4	
			data_hi_ld <= '0';
			data_out_ld <= '0';
			sig_out	<= '0';
			if (sig_in='1') then
			    nextState <= ST4;   -- goto state ST4
			end if;                 -- else remain in state ST3 

	when ST4 =>	data_lo_ld <= '0';	-- RecSecond4Start
			data_hi_ld <= '1';
			data_out_ld <= '0';
			sig_out	<= '0';
			nextState <= ST4a;      -- goto state ST4a
			
	when ST4a =>	data_lo_ld <= '0';	-- RecSecond4Start
			data_hi_ld <= '1';
			data_out_ld <= '0';
			sig_out	<= '0';
			nextState <= ST5;      -- goto state ST5

	when ST5 =>	data_lo_ld <= '0';	-- RecSecond4End
			data_hi_ld <= '0';
			data_out_ld <= '0';
			sig_out	<= '0';
			if (sig_in='0') then
			   nextState <= ST6;   -- goto state ST6
			end if;                -- else remain in state ST5  

	when ST6 =>	data_lo_ld <= '0';	-- Send8Start
			data_hi_ld <= '0';
			data_out_ld <= '1';
			sig_out	<= '0';
			nextState <= ST7;      -- goto state ST7			  

	when ST7 =>	data_lo_ld <= '0';	-- Send8End	
			data_hi_ld <= '0';
			data_out_ld	<= '0';
			sig_out	<= '1';
			nextState <= ST7a;      -- goto state ST7a
	when ST7a => 	data_lo_ld <= '0';	-- Send8End	
			data_hi_ld <= '0';
			data_out_ld	<= '0';
			sig_out	<= '1';					
			nextState <= ST0;      -- goto state ST0

	when others =>  data_lo_ld <= '0';		
			data_hi_ld <= '0';
			data_out_ld <= '0';
			sig_out	<= '0';
			nextState <= ST0;      -- goto state ST0
    end case;

end process;


end fsm;