Ujjwal Guin, Ph.D., IEEE Senior Member

Godbold Associate Professor
Co-Graduate Program Officer (Co-GPO)
Department of Electrical and Computer Engineering
Auburn University
325 Broun Hall, Auburn, AL 36849-5201, USA
Email: ujjwal.guin at auburn dot edu
Phone: (334) 844-1835 (Office)
[Curriculum vitae][Google Scholar][Research Gate]

Detection and Avoidance of Counterfeit ICs


With the advent of globalization and the resulting horizontal integration, present-day electronic component supply chain has become extremely complex and calls for immediate solutions to eliminate counterfeit integrated circuits (ICs). Such counterfeit ICs - recycled, remarked, overproduced, defective, cloned, or tampered - have raised serious concerns regarding the safety and security of our critical infrastructures, such as, military systems, financial infrastructures, transportation, communication, medical systems, and many more applications. Information Handling Services Inc. reported that the incidence of counterfeit parts has quadrupled since 2009, which represents $169 billion in potential annual risk for the global electronics supply chain.

The detection and avoidance approaches for counterfeit ICs are broadly classified into four different categories. First, there are several standards (e.g., AS6171, AS5553, CCAP-101, IDEA-STD-1010) in practice which recommend different physical and electrical tests for the detection purpose. The goal of these tests is to identify defects and anomalies (see details in Chapter 3 of our book, or AS6171/1) present in those counterfeit ICs. However, there are severe limitations for implementing these tests due to prohibitively excessive test times, test costs, low detection capability, and lack of automation. Second, researchers have proposed several schemes based-on statistical data analysis. However, these solutions provide limited accuracy when the chips are used for a short period of time, and often required authentic samples to train the model making it infeasible especially obsolete parts. Third, on-chip sensors have been proposed as an alternative to the conventional test methods for efficient detection of these ICs. Unfortunately, these solutions cannot be used for the parts already in the market. Finally, DNA markings are commercially available to provide traceability for electronic parts. However, a complex (detailed) authentication process have made its application limited in practice.

In this project, we are working on developing several solutions to ensure the efficient detection of these counterfeit ICs. Prof. Guin has co-authored a book, Counterfeit Integrated Circuits: Detection and Avoidance. He is an active participant in the SAE International's G-19A Test Laboratory Standards Development Committee. He is currently the subgroup lead of Suspect/Counterfeit Test Evaluation Method AS6171/1. He has developed a web-based tool (CDC Tool) to evaluate the effectiveness of different test methods used for counterfeit IC detection. SAE International has acquired this tool from University of Connecticut in 2017.

Project Sponsors

We are thankful to our sponsors for supporting our research.

Publications

Disclaimer: The pdf files (articles) are copyright protected. Retrieving, copying, or distributing these files are prohibited. You may, however, browse these articles in the same spirit as you read an article in a public library.

Books
  1. M. Tehranipoor, U. Guin, and D. Forte, "Counterfeit Integrated Circuits: Detection and Avoidance", Springer, 2015. [Amazon] [BibTeX: tehranipoor2015counterfeit]
Journal Papers
  1. Z. Collier, U. Guin , J. Sarkis, and J. Lambert, "Decision Model with Quantification of Buyer-Supplier Trust in Advanced Technology Enterprises," in Benchmarking: an International Journal, pp. 1-24, 2021. [Link] [PDF] [BibTeX: collier2021decision]
  2. D. DiMase, Z. A. Collier, J. Muldavin, J. A. Chandy, D. Davidson, D. Doran, U. Guin, J. Hallman, J. Heebink, E. Hall, and Honorable A. R. Shaffer, "Zero Trust for Hardware Supply Chains: Challenges in Application of Zero Trust Principles to Hardware," in National Defense Industrial Association (NDIA), pp. 1-53, 2021. [White Paper] [LINK] [BibTeX: collier2021zero]
  3. P. Chowdhury, U. Guin, A. D. Singh, and V. D. Agrawal, "Estimating Operational Age of an Integrated Circuit," in Journal of Electronic Testing: Theory and Applications (JETTA), pp. 1-16, 2021. [PDF] [BibTeX: chowdhury2021estimating]
  4. P. Cui, J. Dixon, U. Guin, and D. DiMase, "A Blockchain-Based Framework for Supply Chain Provenance", IEEE Access, pp. 157113-157125, 2019. [LINK] [PDF] [BibTeX: cui2019blockchainProvenance]
  5. Y. Zhang and U. Guin, "End-to-End Traceability of ICs in Component Supply Chain for Fighting Against Recycling", Transactions on Information Forensics & Security (TIFS), pp. 767-775, 2019. [LINK] [PDF] [BibTeX: zhang2019end]
  6. U. Guin, D. Forte, and M. Tehranipoor, “Design of Accurate Low-Cost On-Chip Structures for protecting Integrated Circuits against Recycling," IEEE Transactions on VLSI Systems (TVLSI), pp. 1233-1246, 2015. [LINK] [PDF] [BibTeX: guin2015design]
  7. U. Guin, K. Huang, D. DiMase, J. M. Carulli Jr., M. Tehranipoor, and Y. Makris, “Counterfeit Integrated Circuits: A Rising Threat in the Global Semiconductor Supply Chain," Proceedings of the IEEE, pp. 1207-1228, 2014. [LINK] [PDF] [BibTeX: guin2014counterfeitProc] (cited in "White House 100-Day Reviews under Executive Order 14017" on "Building Resilient Supply Chains, Revitalizing American Manufacturing, and Fostering Broad-Based Growth")
  8. U. Guin, D. DiMase, and M. Tehranipoor, “Counterfeit Integrated Circuits: Detection, Avoidance, and the Challenges Ahead," Journal of Electronic Testing: Theory and Applications (JETTA), pp. 9-23, 2014. [LINK] [PDF] [BibTeX: guin2014counterfeitJETTA] (Most downloaded article in 2014)
  9. U. Guin, D. DiMase, and M. Tehranipoor, “A Comprehensive Framework for Counterfeit Defect Coverage Analysis and Detection Assessment," Journal of Electronic Testing: Theory and Applications (JETTA), pp. 25-40, 2014. [LINK] [PDF] [BibTeX: guin2014comprehensive]
Conference Papers
  1. W. Wang, U. Guin, and A. Singh, “A Zero-Cost Detection Approach for Recycled ICs using Scan Architecture," in VLSI Test Symposium (VTS), pp. 1-6, 2020. [LINK] [PDF] [BibTeX: wang2020zero]
  2. U. Guin, W. Wang, C. Harper, and A. D. Singh, “Detecting Recycled SoCs by Exploiting Aging Induced Biases in Memory Cells," in IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 72-80, 2019. [LINK] [PDF] [BibTeX: guin2019detecting]
  3. P. Chowdhury, U. Guin, A. D. Singh and V. D. Agrawal, “Two-Pattern ΔIDDQ Test for Recycled IC Detection," in International Conference on VLSI Design (VLSID), pp. 82-87, 2019. [LINK] [PDF] [BibTeX: chowdhury2019two]
  4. M. Alam, S. Chowdhury, M. Tehranipoor, and U. Guin, “Robust, Low-Cost, and Accurate Detection of Recycled ICs using Digital Signatures," in IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 209-214, 2018. [LINK] [PDF] [BibTeX: alam2018robust]
  5. U. Guin, “Efficient Strategies for Detection and Avoidance of Counterfeit ICs," IEEE North Atlantic Test Workshop (NATW), pp. 1-5, 2017. [PDF] [BibTeX: guinefficient]
  6. B. Shakya, U. Guin, M. Tehranipoor and D. Forte, “Performance Optimization for On-Chip Sensors to Detect Recycled ICs," IEEE International Conference on Computer Design (ICCD), pp. 289-295, 2015. [LINK] [BibTeX: shakya2015performance]
  7. U. Guin,
  8. U. Guin, X. Zhang, D. Forte, and M. Tehranipoor, “Low-Cost On-Chip Structures for Combating Die and IC Recycling," Design Automation Conference (DAC), pp. 1-6, 2014. [LINK] [BibTeX: guin2014low]
  9. U. Guin, D. Forte, D. DiMase, and M. Tehranipoor, “Counterfeit IC Detection: Test Method Selection Considering Test Time, Cost, and Tiel Level Risk," GOMACTech, pp. 1-4, 2014. [PDF] [BibTeX: guin2014icdetect]
  10. U. Guin, D. Forte, and M. Tehranipoor, “Low-cost On-Chip Structures for Combating Die and IC Recycling," GOMACTech, pp. 1-3, 2014. [PDF] [BibTeX: guin2014cost]
  11. U. Guin, D. Forte, and M. Tehranipoor, “Anti-Counterfeit Techniques: From Design to Resign," IEEE Microprocessor Test Verification (MTV), pp. 89-94, 2013. [LINK] [BibTeX: guin2013anti]
  12. U. Guin and M. Tehranipoor, “CDIR: Low-Cost Combating Die/IC Recycling Structures," DMSMS, 2013. (Extended Abstract) [LINK] [BibTeX: guin2013cdir]
  13. U. Guin and M. Tehranipoor, “On Selection of Counterfeit IC Detection Methods," IEEE North Atlantic Test Workshop (NATW), pp. 1-5, 2013. [PDF] [BibTeX: guin2013selection] (Received Best Paper Award)
  14. U. Guin, and M. Tehranipoor, “Counterfeit Detection Technology Assessment," GOMACTech, pp. 1-4, 2013. [PDF] [BibTeX: guin2013asses]
  15. N. Murphy, U. Guin, and M. Tehranipoor, “Counterfeit Detection Technology Assessment," DMSMS & Standardization, 2012. [BibTeX: murphy2012asses]
Technical Reports
  1. U. Guin, M. Tehranipoor, D. DiMase, and M. Megrdician, “Counterfeit IC Detection and Challenges Ahead," ACM SIGDA, pp. 1-5, 2013. [PDF] [BibTeX: guin2013counterfeit]