Ujjwal Guin is currently an Associate Professor at the Department of Electrical and Computer Engineering, Auburn University. He received his Ph.D. degree from the University of Connecticut in 2016. He is actively involved in projects in the field of Hardware Security and Trust, Supply Chain Security, Cybersecurity, and VLSI Design and Test. He has developed several on-chip structures and techniques to improve the security, trustworthiness, and reliability of integrated circuits. He is a co-author of the book "Counterfeit Integrated Circuits: Detection and Avoidance". He has authored several journal articles and refereed conference papers. His projects are sponsored by the United States Secret Service, National Science Foundation (NSF), Air Force Research Laboratory (AFRL), and Auburn University.

Dr. Guin was actively involved in developing a web-based tool, Counterfeit Defect Coverage Tool (CDC Tool), http://www.sae.org/standardsdev/cdctool/. This tool has been adopted in "AS6171: Test Methods Standard; General Requirements, Suspect/Counterfeit, Electrical, Electronic, and Electromechanical Parts" for the basis of test method selection and evaluation of test effectiveness. He serves on the SAE International G-19A Test Laboratory Standards Development Committee and G-32 Cyber-Physical Systems Security Committee. He currently serves or has served several technical program committees in several reputed conferences, such as DAC, HOST, VTS, PAINE, VLSID, GLSVLSI, ISVLSI and Blockchain. He is the Vice Program Chair of PAINE, Finance Chair of HOST and Student Activities Chair of VTS. He is a senior member of IEEE and member of ACM.

Dr. Guin's current research focuses on:

• Detection and Avoidance of Counterfeit ICs
• Prevention of the Piracy of Intellectual Properties (IP)
• Design, Test, and Security of Skyrmion Logic Circuits
• Blockchain for Supply Chain Security and Implementation of Zero-Knowledge Proofs
• Trusted Electronic Systems
• Heterogeneous Integration