Books

M. Tehranipoor, U. Guin, and D. Forte, "Counterfeit Integrated Circuits: Detection and Avoidance", Springer, 2015. [Springer ][Amazon]

Book Chapters

U. Guin, and M. Tehranipoor, "Obfuscation and Encryption for Securing Semiconductor Supply Chain", in Hardware Protection through Obfuscation, Springer, 2017. [Springer ]

Journal Papers

M. Alam, M. Tehranipoor, and U. Guin, “TSensors Vision, Infrastructure and Security Challenges in Trillion Sensor Era: Current Trends and Future Directions”, Journal of Hardware and Systems Security (HaSS), 2017. [LINK]
M. Tehranipoor, U. Guin, and S. Bhunia, “Invasion of the Hardware Snatchers: Cloned Electronics Pollute the Market”, IEEE Spectrum, 2017. [LINK]
U. Guin, S. Bhunia, D. Forte, and M. Tehranipoor, “SMA: A System-Level Mutual Authentication for Protecting Electronic Hardware and Firmware”, IEEE Transactions on Dependable and Secure Computing (TDSC), 2016. [LINK]
U. Guin, Q. Shi, D. Forte, and M. Tehranipoor, “FORTIS: A Comprehensive Solution for Establishing Forward Trust for Protecting IPs and ICs”, ACM Transactions on Design Automation of Electronic Systems (TODAES), 2016. [LINK]
U. Guin, D. Forte, and M. Tehranipoor, “Design of Accurate Low-Cost On-Chip Structures for protecting Integrated Circuits against Recycling”, IEEE Transactions on VLSI Systems (TVLSI), 2015. [LINK]
U. Guin, K. Huang, D. DiMase, J. M. Carulli Jr., M. Tehranipoor, and Y. Makris, “Counterfeit Integrated Circuits: A Rising Threat in the Global Semiconductor Supply Chain”, Proceedings of the IEEE, 2014. [LINK]
U. Guin, D. DiMase, and M. Tehranipoor, “Counterfeit Integrated Circuits: Detection, Avoidance, and the Challenges Ahead”, Journal of Electronic Testing: Theory and Applications (JETTA), 2014. [LINK] (Most downloaded article in 2014)
U. Guin, D. DiMase, and M. Tehranipoor, “A Comprehensive Framework for Counterfeit Defect Coverage Analysis and Detection Assessment”, Journal of Electronic Testing: Theory and Applications (JETTA), 2014. [LINK]

Conference Papers

U. Guin, A. Singh, M. Alam, J. Canedo, and A. Skjellum, “A Secure Low-Cost Edge Device Authentication Scheme for the Internet of Things”, in International Conference on VLSI Design, 2018 (To Appear).
U. Guin, “Efficient Strategies for Detection and Avoidance of Counterfeit ICs”, IEEE North Atlantic Test Workshop (NATW), 2017. [PDF]
U. Guin, Z. Zhou, and A. Singh, “A Novel Design-for-Security (DFS) Architecture to Prevent Unauthorized IC Overproduction”, IEEE VLSI Test Symposium (VTS), 2017. [LINK]
B. Shakya, U. Guin, M. Tehranipoor and D. Forte, “Performance Optimization for On-Chip Sensors to Detect Recycled ICs”, IEEE International Conference on Computer Design (ICCD), 2015. [LINK]
U. Guin, X. Zhang, D. Forte, and M. Tehranipoor, “Low-Cost On-Chip Structures for Combating Die and IC Recycling”, Design Automation Conference (DAC), 2014. [LINK]
U. Guin, D. Forte, D. DiMase, and M. Tehranipoor, “Counterfeit IC Detection: Test Method Selection Considering Test Time, Cost, and Tiel Level Risk”, GOMACTech, 2014. [PDF]
U. Guin, D. Forte, and M. Tehranipoor, “Low-cost On-Chip Structures for Combating Die and IC Recycling”, GOMACTech, 2014. [PDF]
U. Guin, D. Forte, and M. Tehranipoor, “Anti-Counterfeit Techniques: From Design to Resign”, IEEE Microprocessor Test Verification (MTV), 2013. [LINK]
U. Guin and M. Tehranipoor, “CDIR: Low-Cost Combating Die/IC Recycling Structures”, DMSMS, 2013.(Extended Abstract) [LINK]
U. Guin, T. Chakraborty, and M. Tehranipoor, “Functional Fmax Test-Time Reduction using Novel DFTs for Circuit Initialization”, IEEE Int. Conference on Computer Design (ICCD), 2013. [LINK]
U. Guin, T. Chakraborty, and M. Tehranipoor, “Novel DFTs for Circuit Initialization to Reduce Functional Fmax Test Time”, IEEE North Atlantic Test Workshop (NATW), 2013. [PDF]
U. Guin and M. Tehranipoor, “On Selection of Counterfeit IC Detection Methods”, IEEE North Atlantic Test Workshop (NATW), 2013. [PDF] (Received Best Paper Award)
U. Guin, and M. Tehranipoor, “Counterfeit Detection Technology Assessment”, GOMACTech, 2013. [PDF]
N. Murphy, U. Guin, and M. Tehranipoor, “Counterfeit Detection Technology Assessment”, DMSMS & Standardization, 2012.
U. Guin and C. -H. Chiang, “Design for Bit Error Rate Estimation of High Speed Serial Links”, IEEE VLSI Test Symposium (VTS), 2011.

Technical Reports

U. Guin, M. Tehranipoor, D. DiMase, and M. Megrdician, “Counterfeit IC Detection and Challenges Ahead”, ACM SIGDA, 2013. [PDF]

Thesis

[T1] U. Guin, “Establishment of trust and integrity in modern supply chain from design to resign”, PhD Thesis, University of Connecticut, CT, 2016. [LINK]
[T2] U. Guin, “Design for Bit Error Rate Estimation of High Speed Serial Links”, Masters Thesis, Temple University, PA, 2010.

Patents

M. Tehranipoor, U. Guin, and D. Forte, “A Comprehensive Framework for Protecting Intellectual Property in the Semicondor Industry”, Filed, 2017.
 Department of Electrical and Computer Engineering | Auburn University | Auburn, Alabama 36849-5201 | (334) 844-1835 | ujjwal.guin@auburn.edu
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