Ujjwal Guin is currently an Assistant Professor at the Department of Electrical and Computer Engineering, Auburn University. He received his Ph.D. degree from the University of Connecticut in 2016. He is actively involved in projects in the field of Hardware Security and Trust, Supply Chain Security, Cybersecurity, and VLSI Design and Test. He has developed several on-chip structures and techniques to improve the security, trustworthiness, and reliability of integrated circuits. His current research interests include Hardware Security & Trust, Blockchain, Supply Chain Security, Cybersecurity, and VLSI Design & Test. He is a co-author of the book "Counterfeit Integrated Circuits: Detection and Avoidance". He has authored several journal articles and refereed conference papers. His projects are sponsored by the National Science Foundation (NSF), Air Force Research Laboratory (AFRL), and Auburn University.
Prof. Guin was actively involved in developing a web-based tool, Counterfeit Defect Coverage Tool (CDC Tool), http://www.sae.org/standardsdev/cdctool/. This tool has been adopted in "AS6171: Test Methods Standard; General Requirements, Suspect/Counterfeit, Electrical, Electronic, and Electromechanical Parts" for the basis of test method selection and evaluation of test effectiveness.
Prof. Guin serves on the organizing committees VLSI Test Symposium (VTS) and the IEEE International Conference on Physical Assurance and Inspection of Electronics (PAINE). He has been serving on the technical program committees in several reputed conferences, such as DAC, HOST, VTS, PAINE, VLSID, GLSVLSI, ISVLSI and Blockchain. He is an active participant in the SAE International G-19A Test Laboratory Standards Development Committee and G-32 Cyber-Physical Systems Security Committee. He is a member of both the IEEE and ACM.