ELEC 4200 Digital System Design

Description: Description: Description: Description: Description: Description: Description: Description: Description: link to Professor Roth web page about his text book (with errata)Lecture: 3:00-3:50pm Wednesday & Friday (Broun 306)

Lab (Broun 320):

Section 1: 4:00-6:50pm Monday

Section 2: 5:00-7:50pm Wednesday

 

General Syllabus

 

Spring 2013 Syllabus

 

 

Some Reference Material

VHDL Review/Overview

Other reference suggestions

Link to free ISE WebPack for your own PC if you want to simulate & synthesize before the lab session

Lecture Notes:

Logic Design Review:

Combinational & Sequential Design Process

Flip-flops and Latches

FPGAs:

Overview of FPGAs

Programming Technologies and PALs and PLDs

More Details on FPGAs and Overview of LFSRs

Configuration Interfaces and Configuration for Virtex I & Spartan II and Spartan 3 Configuration

Overview of Boundary Scan and the Boundary Scan Interface in Spartan-2 FPGAs (for Spartan-3 BS interface see JTAG section in Spartan 3 Configuration)

PicoBlaze Overview and PicoBlaze Manual and Userís Guide

VHDL:

HDLs in the Design Process

VHDL Entities, Architectures, and Processes

VHDL Names, Signals, and Attributes

VHDL Operators

VHDL Constructs

VHDL Hierarchical Modeling

VHDL Modeling Guidelines

Parameterized RAM Modeling

Test Benches

VHDL FSM Modeling

VHDL Sequential Logic Modeling

Verilog

ASIC/FPGA Synthesis:

Dr. Nelsonís Lecture October 2009

 

Lab Exercises:

Lab #0 - (1/14 & 1/16) Introduction to lab hardware & software Lab #0 Tutorial

Lab #1 - (1/28 & 1/30) Combinational Logic Design Using Schematic Capture

Lab #2 - (2/4 & 2/6) Sequential Logic Design Using Schematic Capture

Lab #3 - (2/11 & 2/12) Combinational Logic Design Using VHDL

Lab #4 - (2/18 & 2/20) Sequential Logic Design Using VHDL Jiaís tutorial on Post Place & Route Simulation

Lab #5 - (2/25 & 2/27) Parameterized VHDL Universal Register/Counter

Lab #6 - (3/4 & 3/5) Parameterized VHDL Register File Design with Test Bench

Lab #7 - (3/18 & 3/20) Hierarchical VHDL Modeling of Manually Controlled Display System

Lab #8 - (3/25 & 3/27) Boundary Scan Interface Controlled Display System - Gefuís tutorial on communicating with BS Hint: One solution to bleeding and/or dim display problem is to add an 11-bit register at the output (for the 7 segments and 4 enable values) which is enabled by the output of the digital 1-shot (this will hold the 7-segment value plus the valid enable for the maximum amount of time until the next value is ready for display for good brightness with minimum bleeding).

Lab #9 - (4/1 & 4/3) PicoBlaze Programming, Simulation and Synthesis Tutorial for PicoBlaze and the tutorial files (PicoBlaze.zip)

Lab #10 - (4/8 - 4/24) PicoBlaze Controlled Display System

 

Reference Material for Lab Exercises:
Link to free ISE WebPack for your own PC if you want to simulate & synthesize before the lab session

ISE Quick Start Guide

Spartan 3 PCB Reference Manual

Spartan 3 PCB Schematic

Xilinx Spartan 3 Data Sheet

 

Additional Tutorials for Lab Exercises:

FAQs by Gefu Xu and Jie Qin

ModelSim Tips by Jie Qin

Overview of FPGA Editor

Adding Probes in FPGA Editor

Overview of PACE

 

Detailed manuals for ISE can be found on the lab computers in C:\Xilinx\doc\usenglish\books\manuals.pdf

Link to free ISE WebPack and link to free Student Version of ModelSim for your own PC if you want to simulate & synthesize before the lab session