use work.qsim_logic.all;

entity regfile is
port(
     clock    : in bit;
     regwr    : in bit;
     wrreg    : in bit_vector(3 downto 0);
     rr1      : in bit_vector(3 downto 0);
     rr2      : in bit_vector(3 downto 0);
     wrdata   : in bit_vector(15 downto 0);
     rd1      : out bit_vector(15 downto 0);   
     rd2      : out bit_vector(15 downto 0)  
    );
end regfile;

architecture reg of regfile is
type regs is array(0 to 15) of bit_vector(15 downto 0);
signal reg : regs;
 
begin
process(clock)

begin
if clock'event and clock = '1' then
 if regwr = '1' then
   if (wrreg = "0000") then
    reg(to_integer('0' & wrreg)) <= "0000000000000000"; -- Register 0 hardwired to zero.
   else
    reg(to_integer('0' & wrreg)) <= wrdata;
   end if;
 end if;
end if;

end process;

rd1 <= reg(to_integer('0' & rr1));
rd2 <= reg(to_integer('0' & rr2));

end;