ELEC 5250/6250/6256 - Computer-Aided Design of Digital Circuits

Fall Semester, 2018

Instructor: Victor P. Nelson, Professor of ECE

Syllabus: ELEC 5250/6250/6256

Important Dates:

·         Labor Day Holiday: Monday, September 3

·         Midterm Exam (date TBA)

·         Fall Break:  Thursday-Friday, October 11-12

·         Thanksgiving Holidays: Monday-Friday, November 19-23

·         Last Class Day: Friday, December 7

·         Final Exam: Wednesday, December 12, 8:00-10:30 a.m.

Homework Assignments:

  1. Wednesday, August 22:   Three-to-four page report describing a commercial ASIC (function, technology, characteristics, CAD tools used, etc.) This must be some commercial ASIC that has been designed for a particular application within the past two years. Do not report on a “platform” FPGA/ASIC, microcontroller, or IP block – report on an ASIC produced for a particular application.
  2. Friday, August 24: (Prerequisite review) Modulo-6 counter design
  3. Thursday, September 6: Modulo-6 counter Verilog models
  4. Monday, September 10:    PART 1: Modulo-6 counter simulations (do file)
  5. Thursday, September 13:  PART 2: Modulo-6 counter simulations (testbench)
  6. Wednesday, September 19: Binary divider Verilog model (draft models/no grade)
  7. Monday, September 24:  Binary divider Verilog model and simulation

Wednesday, October 3: Midterm Quiz

  1. Friday, October 5: Synthesis of Verilog model(s)
  2. Tuesday, October 15 (11:00 am): Timing simulation and analysis
  3. Monday, October 29 (in class):  Block layout from Innovus

Course Topics & Lecture Slides (linked PDF files):

  1. SoCs and ASICs
  2. ASIC Technologies and Design
  3. ASIC Cost
  4. ASIC Design Process
  5. Verilog modeling for ASIC design
  6. Simulation of Verilog models
  7. Verilog testbenches
  8. Modular Verilog models
  9. Synthesis with Synopsys Design Compiler
  10. Post-synthesis simulation with delay data
  11. CMOS IC fabrication processes
  12. Physical design of blocks of standard cells
  13. Faults and test-pattern generation
  14. Automatic test-pattern generation and fault simulation
  15. Design for testability (DFT)
  16. Advantest T2000 tester  
  17. Built-in Self Test
  18. Top-Level Chip Layout in Virtuoso
  19. Post-Layout Verification with Calibre
  20. Post-Layout Simulation with ADiT
  21. AMI06 Technology and Top-Level Layout
  22. Design with Intellectual Property Cores

Reference Material:

 

Useful CAD Tool Links:

·         Mentor Graphics ADK standard cell HDL model files:

adk.vhd (VHDL cell models)

adk_comp.vhd (VHDL component declaration package)

adk.v (Verilog cell models)

On linux server at

            /linux_apps/ADK3.1/technology

gdk.vhd (VHDL cell models)

gdk_comp.vhd (VHDL component declaration pkg),

gdk.v (Verilog cell models)

On linux server at

/linux_apps/mentor/pyxis/Pyxis_SPT_HEP/ic_reflibs/external_libs/GDKgates/GDKgates_utilities/hdl_libs

·         AU Student-Authored Tutorials on Mentor Graphics Tools, ASIC Design Kit (ADK) Standard Cells, Scan-Based Design-for-Test

·         Haihua Yan/Gefu Xu

·         Ayoush Dixit/Harshit Poladia

 

VHDL Links

·        Nandland” FPGA/VHDL/Verilog Tutorials