ELEC 5250/6250 - Computer-Aided Design of Digital Circuits

Fall Semester, 2009

Instructor: Victor P. Nelson, Professor of ECE

Syllabus: ELEC 5250/6250

Reference Material:

• Application-Specific Integrated Circuits, Michael J. S. Smith, Addison Wesley Longman, Inc., 1997 (2008 Soft Cover edition available at Amazon.com and other places) http://www.edacafe.com/books/ASIC/ASICs.php
• Other resources at EDACafe: http://www.edacafe.com/
• Professor Smith's "ASICs... the Web Site"

Course Lectures & Related Slides:

• Lecture 1 (8/18/09) - ASIC Technology Overview
• Lecture 2 (8/20/09) - ASIC Cost Issues
• Lecture 3 (8/25/09) - ASIC Design Flow
• Lecture 4 (8/27/09) – VHDL For Synthesis (1 - Introduction)
• Lecture 5 (9/01/09) – VHDL For Synthesis (2 – Combinational Logic Circuits)
• Lecture 6 (9/03/09) – VHDL For Synthesis (3 – Sequential Circuits)
• Lecture 7 (9/08/09) – VHDL For Synthesis (4 – Finite State Machines)
• Lecture 8 (9/10/09) – VHDL For Synthesis (5 – Simulation with ModelSim)
• Lecture 9 (9/15/09) – VHDL For Synthesis (6 – Design Examples)
• Lecture 9 (9/15/09) – VHDL Simulation Testbenches (NO CLASS TUESDAY, 9/15/09)
• Lecture 10 (9/17/09) – Dr. Stroud (Fault models, DFT) – Slides on ELEC 5280 Page
• Lecture 11 (9/22/09) – Dr. Stroud (DFT, BIST)
• Lecture 12 (9/24/09) – Automated Synthesis with Leonardo and Synopsys
• Lecture 13 (9/29/09) – Automated Synthesis with Leonardo and Synopsys (continued)
• Lecture 14 (10/01/09) – System/circuit timing analysis
• Lecture 15 (10/06/09) - System/circuit timing analysis (continued)
• Lecture 16 (10/08/09) – Synthesis with script files (Synopsys Design Compiler)
• Sample DC setup and script files
• Lecture 17 (10/13/09) – Mentor Graphics Design Architect-IC
• Lecture 18 (10/15/09) – CMOS Fabrication Process
• Lecture 19 (10/20/09) - Standard Cell Block Layout (IC Station)
• Lecture 20 (10/22/09) – Design rule checking, standard cell block layout in SOC Encounter
• Lecture 21 (10/27/09) - Using Calibre for LVS and PEX
• Lecture 22 (10/29/09) - Post-layout simulation with Mach TA.
• Mid-term exam: Submit at 8:00 a.m. on Thursday, November 5.
• No class on Tuesday, November 3.
• Lecture 23 (11/5/09) - Top-level chip layout.
• Lecture 24 (11/10/09) – Top-level chip layout (continued), post-layout simulation with ADiT
• Lecture 25 (11/12/09) – Post-layout simulation with ADiT.
• Lecture 26 (11/17/09) - ASIC test and automatic test pattern generation (ATPG)
• Lecture 27 (11/19/09) - ASIC test: ATPG (Fastscan, Flextest), Design for test (DFT) – DFTAdvisor
• Lecture 28 (12/1/09) – Boundary scan design
• Lecture 29 (12/3/09) – Built-in self test
• FINAL EXAM – Take home, to be submitted no later than 10:30 a.m., Wednesday, December 9 (the scheduled final exam period).
• ELEC 5250 Final Exam
• ELEC 6250 Final Exam

Homework Assignments:

• Tuesday, August 25: Two-page report on a commercial ASIC (function, technology, characteristics, CAD tools used, etc.)
• Thursday, August 27: Modulo-6 counter (gate-level design review)
• Thursday, September 3: Modulo-6 counter (VHDL behavioral and structural models)
• adk.vhd file adk_comp.vhd file
• Thursday, September 10: Modulo-6 counter (Simulations of behavioral and structural models, with “do file” and testbench)
• Thursday, September 17: Binary division circuit (Drafts of the four models – for instructor feedback)
• Thursday, September 24: Final models, test benches/do files, and top-level simulation
• Thursday, October 1: Synthesize the modulo-6 counter and divider
• Tuesday, October 13: Timing analysis (5250 – counter, 6250 – divider)
• Tuesday, October 20: Synthesis with a script, using Synopsys Design Compiler
• Thursday, October 29: Automated place and route in IC Station
• Friday, November 13: Top-level chip design (CANCELLED)
• Tuesday, November 17: Post-layout simulation with ADiT

Useful CAD Tool Links:

• Auburn ECE "Computing Tools" Resources
• Designing Standard Cells ASICs with the ASIC Design Kit (ADK) and Mentor Graphics Tools
• To access Mentor Graphics IC Flow documentation on a UNIX system, enter the command:  mgcdocs _bk_icflow.pdf
• Mentor Graphics Tools Seminar

· AU Student-Authored Tutorials on Mentor Graphics Tools, ASIC Design Kit (ADK) Standard Cells, Scan-Based Design-for-Test

· Haihua Yan/Gefu Xu

· Ayoush Dixit/Harshit Poladia

• chiptalk.org – IC Design and EDA Tools Resources
• Modelsim PE Student Edition Download: http://www.model.com/resources/student_edition/download.asp
• Virginia Tech “VLSI Design World” (Cell Libraries, CAD Tool Tutorials)
• North Carolina State University – EDA Wiki (NCSU Cadence Design Kit – CDK & Tutorials)
• Santa Clara University – VLSI CAD Tutorials

VHDL Links

• VHDL Overview (ELEC 5200/6200)
• Professor Stroud's ELEC 4200 VHDL Resources
• EDA Industry Working Groups for VHDL, Verilog, and related standards
• Hamburg VHDL Archive (Good source of VHDL documentation, models & tools)
• A comparison of VHDL andVerilog with examples of equivalent models in each language
• A comprehensive set of overviews of VHDL, Verilog, System C, PERL, and TCL/TK
• VHDL Cookbook - a 111 page PDF pre-publihed version of The Designer's Guide to VHDL
• A VHDL tutorial (by Weijun Zhang, U.C. Riverside) with good examples and links to reference and related material