ELEC 5250/6250/6256 - Computer-Aided Design of Digital Circuits

Fall Semester, 2017

Instructor: Victor P. Nelson, Professor of ECE

Syllabus: ELEC 5250/6250/6256

Course Lectures & Related Slides (linked PDF files):

Homework Assignments:

                                        Simulate Modulo-6 counter with a testbench

·         Wednesday, September 20:  Verilog divider model (for instructor feedback)

·         Friday, September 22: Verilog divider model with simulations

·         Monday, October 2: Synthesis of Modulo-6 counter and Divider

·         Monday, October 9: Post-synthesis simulation with timing data

·         Wednesday, October 25: Physical layout with Encounter

·         Wednesday, November 1: ATPG and Fault Simulation

·         Wednesday, November 8: Design for Testability

·         Wednesday, November 29: Post-Layout Verification

·         Monday, December 11: Final Exam Project

            ELEC 5250 Final Project

            ELEC 6250/6256 Final Project

Reference Material:


Useful CAD Tool Links:

·         Mentor Graphics ADK standard cell HDL model files:

adk.vhd (VHDL cell models)

adk_comp.vhd (VHDL component declaration package)

adk.v (Verilog cell models)

On linux server at


gdk.vhd (VHDL cell models)

gdk_comp.vhd (VHDL component declaration pkg),

gdk.v (Verilog cell models)

On linux server at


·         AU Student-Authored Tutorials on Mentor Graphics Tools, ASIC Design Kit (ADK) Standard Cells, Scan-Based Design-for-Test

·         Haihua Yan/Gefu Xu

·         Ayoush Dixit/Harshit Poladia


VHDL Links

·        Nandland” FPGA/VHDL/Verilog Tutorials