7. Modern CMOS Transistor Physics Using Performance Parametric Analysis

7.1. Objectives

The objectives for this project are:

  • understand CMOS transistor electrical characteristics, Id-Vg, Id-Vd
  • understand body effect
  • extract threshold voltage, subthreshold swing, Ion, Ioff
  • quantify impact of mobility choices on Id-Vg and Id-Vd, velocity saturation in particular
  • quantify impact of gate length
  • quantify impact of poly gate depletion
  • quantify impact of gate oxide dielectric constant
  • quantify NMOS and PMOS differences
  • quantify the impact of halo doping on Id-Vg and Id-Vd, Vth, SS, Ion, Ioff
  • understand drain-induced-barrier lowering through examining Id-Vg for different Vds, and internal details, e.g. potential contours, surface potential, and electron current stream traces

7.2. Required Programs

  • sde
  • sdevice
  • tecplot_sv
  • inspect
  • swb

7.3. Basic Requirements (Reduced)

Except for the halo doping part, all other parts of this project have been done before. When running the inspect programs, in the terminal window you run inspect from, extraction results such as Vth, SS, Ion, Ioff are reported.

You can use swb to manage your project, but you do not have to. It is a powerful tool, but also requires extra effort to be able to write new codes. If it is a task not too different from the example swb I gave you, you can try doing so.

I suggest that you start with just modifying the non-swb codes you have been using for homework. That will be our basic requirement.

Consider using 65nm or 90nm as your nominal short gate length, 180nm or 250nm as mid gate length, and then 1um or 2um as your long gate length. Make 3 folders, one for each gate length. Use Phumob, Enormal, and turn on high field saturation of velocity.

For each gate length:

  • (required) simulate Id-Vg at several Vds, e.g. 50mV, 250mV, 500mV, 1.2V. You can use more Vds values as needed.

    Plot out Id-Vg on both linear and log scales. Make observations and give explanations, analyze relevant .tdr files using tecplot_sv as we have done in the past to support your explanations. Surface plots, i.e. y cut made at say y=1e-7, are useful. For instance, you can compare surface potential plots (at all Vg’s simulated, overlayed) at Vd=Vdd for all 3 gate lengths, to explain why SS at Vd=Vdd is larger in short gate length transistor.

    Use the currentplot commands to plot out the mid channel point’s potential, lateral and vertical field, eVelocity, eDensity etc.

    The subthreshold swing is a good parameter to take notice when examining Vds dependence of Id-Vg.

    Look at how your Vth (use Vd=50mV), SS at Vd=50mV and Vd=Vdd, Ion and Ioff (note for Ion and Ioff, Vg=Vdd and 0, Vd=Vdd) change with gate length.

  • (changed to optional) simulate Id-Vd. Include Vg = 0V.

    Make observations on the slope of Id-Vd, particularly in saturation region.

  • (changed to optional) repeat all simulations, analyze a selected number of .tdr files with velocity saturation turned off. Compare results and explain the difference.

    Discuss how velocity saturation affects Ion, Ioff, Id-Vd (Idsat, and Vdsat in particular), SS, Vth.

7.4. Explorer Further

With some changes to the codes provided, you can investigate more modern CMOS transistor physics. For instance, you can look into a selected number of topics that may interest you at your choice:

7.4.1. Halo Doping

We have seen halo doping’s importance from the simulation results I showed with and without halo doping. You can do this by varying the concentration of halo doping, and run your simulation for 3 gate lengths.

An extreme case will be to set halo doping to a level that is negligible compared to substrate doping level. The sde command file provided has an entry on halo doping level, just modify that, and you can do this yourself.

Examine the tdr files as necessary for deeper insights.

7.4.2. Threshold voltage roll-off

With halo turned off, you can run the Id-Vg at 50mV simulations at many gate lengths from 45nm to 1um, record your Vth and SS, plot them out as a function of gate length. You shall see Vth decrease with gate length, due to the increasing impact of the drain to channel junction on surface potential with decreasing channel length.

Examine the tdr files as necessary for deeper insights.

7.4.3. Reverse Short Channel Effect (RSCE)

With halo turned on, repeat the Id-Vg at 50mV simulations for many gate lengths, e.g. 32nm, 45nm, 65nm, 90nm, 130nm, 180nm, 250nm, 0.5um, 1um, 2um, and 5um. Plot out Vth vs lgate. Vth will first increase with decreasing lgate, and ultimately decrease again at very short gate length.

You may even vary the halo doping level and see how this vth - lgate curve changes.

7.4.4. Body Effect

So far we have set the body bias to zero. You can vary this, and see how your Id-Vg is changed. See how Vth is changed in particular.

7.4.5. Poly Depletion Effect

Poly depletion effect is real and degrades performance by decreasing the effective gate to channel capacitance. Vary the poly gate doping level entry in the sde command file. Look up our text book or IEEE explorer for poly gate doping found in real CMOS technologies. Try a few values from practical levels to very high, e.g. 1e20, 5e20, and see how your Ion and Gm are affected.

Ultimately, you can also use an ideal metal gate in your sde / sdevice command files.

7.4.6. PMOS

While much of our in class discussions / simulations have used NMOS, we should have equally good understanding of PMOS transistor, as CMOS requires both NMOS and PMOS. By swapping all the doping types in the sde command file, you will get a PMOS transistor. You can then repeat simulations.

You want to compare the hVelocity in PMOS with eVelocity in NMOS to understand the difference. Hole mobility is lower than electron mobility, which results in less drive current for the same set of voltages. That difference will also change with channel length due to velocity saturation.

Keep in mind all voltages in your codes need to be multipled by -1.

You can plot out -1 * Id too as the Id for PMOS will be negative. Current going into a terminal is positive in the simulator.

7.4.7. High K gate dielectric

You can also vary the gate oxide material, or simply use silicon diode, but modify the dielectric constant value in the parameter file. A higher epsilon means stronger vertical field effect, which will give you better SS, better Ioff, and better Ion.

7.5. Report

Use as many pages as you need, but think about the best figures to use to support your analysis as well. Every figure you put in the report should serve a purpose. Always make observerations, add analysis, use tdr plots as necessary. Save all your images as png files.

You can use word, latex or any of your favorite word processor.

We will devote this week to this project.

You should have a zipped folder for all your simulations files, ready to run.

Submit your report to me next Monday class time.