Research Papers

Supported by NSF EHCS: Dynamic Vertically Integrated Power-Performance-Reliability Modulation in Embedded Digital Signal Processors

A High Throughput Multiplier Design Exploiting Input based Statistical Distribution in Completion Delays (Draft) VLSI Design 2013

Diagnosing Multiple Slow Gates for Performance Tuning in the Face of Extreme Process Variations. Asian Test Symposium 2011

Path Delay Tuning for Performance Gain in the Face of Random Manufacturing Variations. VLSI Design 2011

Current Sensing Completion Detection for High Speed and Area Efficient Arithmetic APCCAS 2010

A Defect Tolerant and Performance Tunable Gate Architecture for End-of-Roadmap CMOS. DFT 2009