6. Four Resistor MOSFET Amplifier Design (Prelab Help)

6.1. Overview

6.1.1. Fundamentals of MOS Transistor Amplifiers

Consider a MOSFET with a resistor load at the drain, very much like in the resistor-load inverter.

A Vgs change causes an IDS change, which then causes an output voltage change.

So to first order, delta_Vout = delta Ids * Rload.

Voltage gain is thus:

Av = delta_Vout / delta_Vgs = delta_Ids / delta_Vgs * Rload

Delta_Ids/delta_Vgs is called the transconductance gm.

This, however, assumes very small AC input voltage, so that the output voltage change is still small.

So if we make the small signal voltage gain 100, we set the ac input voltage amplitude to 1mV, our ac output voltage amplitude is 100 * 1mV = 0.1V.

6.1.2. Output Voltage Swing - Maximizing It with Bias Point Design

Now if Vin = delta_Vgs = 2V, delta_Vout is not going to have an amplitude of 2V * 100 = 200V. Rather it will saturate as we have demonstrated with a live amplifier.

When Vgs is below threshold, transistor cuts off. So the highest Vout possible is Vdd - 0 * RLoad = Vdd.

When Vgs is very high, the current will increase, and hence pulling down Vout = Vdd - Ids * R.

For an ideal transistor with an ideal knee voltage or drain saturation voltage Vdsat=0V, the best Vout low we can have is when Ids * R = Vdd, and Vout decreases to zero.

If we further assume that the transistor Ids - Vgs is linear, we find that a maximum output voltage swing of Vdd / 2 can be obtained if we choose a DC Vds equal to Vds,dc = Vdd / 2.

The load resistance Rload is simply the ratio of the voltage swing (Vds,dc or Vdd/2) to current swing (Ids,dc):

Rload = Vds,dc/Ids,dc = Vdd / (2 * Ids,dc)

Well, real MOSFETs are not so ideal, as we have seen from measured Ids-Vds curves. The Ids-Vgs relation is not exactly linear but not too far off. The knee voltage or Vdsat at which saturation occurs can be quite a bit above 0V, however. That can be taken into account by setting aside voltage room for the transistor to saturate. The consequence is basically that the lowest Vout will not be zero volt.

6.1.3. Stabilizing DC Bias Point with a Resistor at Source

We have seen that the output voltage and current swing have a lot to do with the DC Ids and DC Vds, which we denote as Ids,dc and Vds,dc. Together, they are called the DC bias point.

There is naturally the need to stabilize the DC bias point against fluctuations of Vdd, temperature, or even transistor threshold voltage or K factor.

Take Vdd increase as an example. It directly translates into Vgs,dc increase, which then increases Ids,dc.

With a resistor between source and ground, an increase of Vdd increases Vg, which then increases Ids.

The Ids increase, however, increases Vs = Ids * Rs. As a result, the resulting Vgs increase is less than the original Vg increase from Vdd increase, simply because Vgs = Vg - Vs.

The Rs resistor is thus said to act as a negative feedback, as it negatively affects the increase of Ids.

6.1.4. AC Operation Consideration of Feedback

For AC signal, we do not necessarily want the large negative feedback.

Say if we want all of the AC input voltage to appear across Vgs, without any drop over Rs, we can just add a large enough capacitor across Rs, so that Rs is shorted out by the capacitor.

6.1.5. Design Procedure

  • choose a reasonable Vs for stability of dc bias, this sets Rs=Vs/Ids,dc

  • find Vgs needed for producing the Ids,dc given.

    In simulation, just connect drain and gate together for saturation operation, force a current of Ids,dc, read the voltage value.

    In the lab, you can run a 2-wire analyzer measurement in the same way you found the threshold voltage from a given threshold current.

  • find Vg = Vgs + Vs.

  • find R1 and R2 that will give the desired Vg,dc.

  • approximately set Vds,dc = (Vdd-Vs)/2.

  • determine Rload = Vds,dc/Ids,dc.

We can consider the finite Vdsat in design and simulation. For first order design, the above simplification works just fine, and greatly simplifies the design.

6.1.5.1. Vs choice Tradeoffs

The good:

larger Vs - more feedback, more stable dc bias point against Vdd, temperature, transistor Vt, transistor K variation etc.

The bad:

More Vs means less voltage room to work with

Vdd - Vs is the available voltage room to work with

Furthermore, for real transistors, we have to choose Vds,dc to be approximately above Vgs,dc-Vt to be in saturation region.

6.1.5.2. R1, R2 choice

R1//R2 (R1 in parallel with R2) will be the input impedance seen by the ac voltage source.

Normally we want R1 // R2 to be large, say around 100 kohms or more.

You do not want small R1//R2 in general, as it will be too much a load for the AC source. A smaller Rin means a large input current requirement, or a “heavy” load. An extreme will be a short circuit load to a source.