create verilog symbol

software: design architect;

input: s1238_scan.v;

output: s1238_veri_sb symbol

see file tree

The verilog description of the circuit can also be represented as an abstract symbol.

1)compile verilog file

-vlib work

-vmap work work

-compile s1238_scan.v with command "vlog s1238_scan.v"


vlib phy_lib_path;

vmap logical_lib phy_lib_path;

These information is saved in the output file (modelsim.ini)

2)create symbol

-create a folder to save symbol (.../s1238/work/s1238_veri_sb)

-run design architect (with command "da" or "adk_da")

-generate symbol

-check symbol

-save symbol