ELEC 4200 Digital System Design

https://images-na.ssl-images-amazon.com/images/I/51ampjqluLL._SX411_BO1,204,203,200_.jpgLecture (Broun 306):

  8:00-8:50 a.m. Tuesday & Thursday

 

Lab (Broun 320):

 Section 001: 4:00-6:50 p.m. Monday

 

Spring 2018 Syllabus;  Lab Handout

 

 

 

Course Review: Textbook Chapters Covered

 

Design and Simulation Software

If you want to simulate & synthesize on your own PC, outside of lab.

Link to free Vivado Design Suite WebPack

Link to free Aldec Active-HDL Student Edition

 

Lecture Notes:

Introduction to ASIC design:

       ASIC Design Flow  (Text: Chaps. 2.1 and 3.4)

Logic Design Review:

       Combinational Circuit Design Process (Chap. 1.1–1.5)

       Sequential Circuit Design Process (Chap. 1.6–1.10)

        Flip-flops and Latches

 

VHDL

   Lecture slides:

VHDL Introduction

VHDL Combinational Logic

VHDL Sequential Logic

VHDL RTL Models

VHDL Memory Models

VHDL Testbenches

VHDL Multiplier Example

 

  VHDL tutorials:

HDLs in the Design Process  

VHDL Entities, Architectures, and Processes

VHDL Names, Signals, and Attributes

VHDL Operators

VHDL Constructs

VHDL Hierarchical Modeling

VHDL Modeling Guidelines

VHDL Parameterized RAM Modeling

VHDL Test Benches  

VHDL FSM Modeling

VHDL Sequential Logic Modeling

VHDL Review/Overview

 

“Nandland” FPGA/VHDL/Verilog Tutorials

 

Verilog

Verilog Overview Slides

Verilog Mini-Tutorial

 

Programmable Logic Devices and FPGAs:

Overview of FPGAs (slides; Text: Chap. 3.4)

Programmable Logic Devices (slides; Text: Chap. 3.1 – 3.3)

PALs and PLDs (document)

Overview of LFSRs

 

  Xilinx Artix-7 FPGA Web Page  (data sheets, user guides, examples, etc.)

          Artix-7 Data Sheet

          7 Series FPGAs Configurable Logic Block User Guide

          Other user guides on Artix-7 web page

  Digilent Nexys4 DDR Artix-7 FPGA Board Web Page and Resources

      Nexys4 DDR Reference Manual 

      Nexys4 DDR Schematic

FPGA Configuration:

Xilinx 7 Series FPGAs Configuration User Guide

Boundary Scan in FPGAs:

Testing and Boundary Scan Overview Slides

Configuration of Spartan-II using Boundary Scan

Spartan 3 Configuration User Guide (see JTAG section)

Boundary Scan Operation via ISE-IMPACT (by Gefu Xu)

 

PicoBlaze:

PicoBlaze KCPSM6 User Manual (Ken Chapman)

PicoBlaze 8-bit Embedded Microcontroller User Guide

PicoBlaze KCPSM6 Assembler and Tutorial files (Lab files: .zip file)

Xilinx PicoBlaze 8-Bit Embedded Microcontroller Web Page

Design Files Download Page

 

Lab Exercises and Homework:

Lab Handout

Special homework (digital logic design review) Due Tuesday, Jan. 16.

Lab #0 Tutorial - (1/15) Introduction to lab hardware & software

               Nexys4 Master Constraints File

Lab #1 - (1/22) Combinational Logic Design Using Logic Equations

-         VHDL model template file for Lab 1

Lab #2 - (1/29) Sequential Logic Design Using Logic Equations

-         VHDL model template file for Lab 2

Lab #3 - (2/5) Combinational Logic Design Using a Behavioral Model

-         Viewing and editing implemented designs in Vivado

Lab #4 - (2/12) Sequential Logic Design Using a Behavioral Model

-         Post-Implementation Timing Simulation

Lab #5 - (2/19) Parameterized VHDL Universal Register/Counter

·        VHDL debounce.vhd circuit model

Lab #6 - (2/26) Parameterized VHDL Register File Design with Test Bench

Lab #7 - (3/5) Hierarchical VHDL Modeling of Manually Controlled Display System

Lab #8 - (3/19) PicoBlaze Programming, Simulation and Synthesis.

·        Links to PicoBlaze User Manual, User Guide, Assembler and Tutorial files provided above.

Lab #9   - (3/26) Interfacing external devices to PicoBlaze via input/output ports.

Lab #10 - (4/2) Interfacing external devices to PicoBlaze via interrupt-driven operation.

Lab #11 - (4/9 to end of semester) PicoBlaze-Controlled Display System – Hint: One solution to bleeding and/or dim display problem is to add an 11-bit register at the output (for the 7 segments and 4 enable values) which is enabled by the write strobe (this will hold the 7-segment value plus the valid enable for the maximum amount of time until the next value is ready for display for good brightness with minimum bleeding).

 

Reference Material for Lab Exercises:

Vivado Quick Start Guide

Digilent Nexys4 DDR Web Page and Resources

      Nexys4 DDR Reference Manual 

      Nexys4 DDR Schematic

Xilinx Artix-7 FPGA Web Page  (data sheets, user guides, examples, etc.)

 

To simulate & synthesize on your own PC before the lab session :

Link to free Vivado Design Suite WebPack

Link to free Aldec Active-HDL Student Edition