Digital Circuit Design for Minimum Transient Energy

Vishwani D. Agrawal
Bell Labs, Murray Hill, NJ 07974
va@research.bell-labs.com

We provide a theoretical basis for reducing or completely eliminating
the energy consumption due to transients in a synchronous digital circuit.
The transient energy is minimized when every gate has no more than one
output transition per clock cycle.  This condition is achieved for a gate
when the gate delay equals or exceeds the maximum difference between path
delays at gate inputs.  In practice, path delays are adjusted either by
increasing gate delays or by inserting delay buffers.  The minimum transient
energy design is obtained when no delay buffer is added.  This design
requires possible increases in gate delays to meet the minimum energy
condition at all gates.  However, the delay of the critical path may be
increased.  In an alternative design, where the critical path delay is not
allowed to increase, delay buffers may have to be added.  A linear program
makes trade-offs between minimum transient energy and critical path delay.
In an extreme design where the delay of the circuit increases three times,
an optimized four-bit ALU circuit consumes 53% peak and 73% average power
in comparison to the unoptimized circuit, as determined by Spice simulation.
This work was done in collaboration with M. L. Bushnell of Rutgers University,
G. Parthasarathy (UC, Santa Barbara) and R. Ramadoss (Lucent).
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Vishwani D. Agrawal is a Distinguished Member of Technical Staff at Bell
Labs, Murray Hill, New Jersey, USA, and a Visiting Professor at Rutgers
University, New Brunswick, New Jersey, USA.  He received a BSc degree from
Allahabad University, Allahabad, India, in 1960, BE degree from University
of Roorkee, Roorkee, India, in 1964, ME degree from the Indian Institute of
Science, Bangalore, India, in 1966, and a PhD degree from the University of
Illinois at Urbana-Champaign in 1971.  In 1986, he was elected an IEEE Fellow
for his contributions to ``probabilistic testing of integrated circuits.''
In 1993, University of Illinois honored him with their Distinguished Alumnus
Award.  In 1998, he received the Harry H. Goode Award of the IEEE Computer
Society for ``innovative contributions to the field of electronic testing.''
He has published 250 papers and five books, and has received five best paper
awards.  His recent text-book, Essentials of Electronic Testing for Digital,
Memory and Mixed-Signal VLSI Circuits, co-authored with M. L. Bushnell has
been published in November 2000.  He holds thirteen U.S. patents.  He has
co-directed 12 PhD theses at major universities.  In 1991 he co-founded
the International Conference on VLSI Design.  He is a former editor-in-chief
(1985-87) of the IEEE Design & Test of Computers and the founding editor-in-
chief (since 1990) of the Journal of Electronic Testing: Theory and
Applications.  He was the program chair for the Fourth IEEE Asian Test
Symposium.  He serves on the ECE Alumni Board of the University of Illinois
and the ECE Advisory Board of the New Jersey Institute of Technology.