Summary for the course:

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Power consumption of a CMOS circuit has emerged as an important design dimension in the nanometer era. The benefits of higher device density and increased clock rates for the modern VLSI system-on-chip (SOC) come at the cost of significantly increased power dissipation. Most VLSI devices and systems must consider low-power design and power management techniques. Requirements are driven by trends including the need to lower system costs (packaging/cooling), longer battery lifetimes for battery‑operated embedded systems, and often conflicting speed and power requirements. 

This course provides an introduction to low power design and optimization techniques that would enable designers to build the ultra‑low power circuits of tomorrow. The instructors will draw from their experience in academia and industry to provide the necessary understanding of sources of power consumption in a CMOS circuit, power estimation techniques at various levels of design abstraction that provide an upfront opportunity to identify design hotspots, architectural and device-level power optimization and management techniques for designing a low‑power SOC, and power issues specific to manufacturing test that impact a modern chip design.

 The course is relevant to chip designers, low power EDA tool developers, academics and researchers working in the area of VLSI design.