ECE SEMINAR: "Can we save energy if we allow limited errors in computing?"

A brief overview of the present understanding of tradeoffs between energy and errors in computing will be presented. The prevailing understanding of a chip’s behavior under large process variations with statistical delay assumptions leads one to conclude that a small number of errors during computation are quite likely as we scale circuit technology and progress further down on Moore’s Law. This conventional understanding is now challenged by a new hypothesis on the behavior of very large CMOS chips in the presence of process variations. A Thought Experiment is presented which leads to this new hypothesis. The hypothesis states that in every large CMOS chip, there exist critical operations points (Frequency, Voltage) such that they divide the 2-D space (F, V) in to two distinct spaces: 1. Error-free operation and 2. Massive errors (i.e. completely inoperable). Attempts at disproving this hypothesis with real physical experiments will be described.  Some consequences of the hypothesis on energy savings in large data centers are also suggested.

Janak H. Patel
Research Professor in the Coordinated Science Laboratory, and Donald Biggar Willet Professor Emeritus in the Department of Electrical and Computer Engineering at the University of Illinois

Janak H. Patel is a research professor in the Coordinated Science Laboratory, as well as the Donald Biggar Willet Professor Emeritus in the Department of Electrical and Computer Engineering at University of Illinois at Urbana-Champaign.

Dr. Patel has made numerous key research contributions in areas that include pipeline scheduling, cache coherence, cache simulation, interconnection networks, online error detection, reliability analysis of memories, design for testability, built-in self-test and fault simulation and automatic test generation. He has supervised more than 85 M.S. and Ph.D. theses and published more than 200 technical papers. He was a founding technical adviser to Nexgen Microsystems that gave rise to the entire line of microprocessors from AMD, and a founder of the successful startup, Sunrise Test, a CAD company now owned by Synopsys.

Dr. Patel received a Bachelor of Science degree in physics from Gujarat University, India, a Bachelor of Technology in electrical engineering from the Indian Institute of Technology (IIT), Madras, and a Master of Science and Ph.D. in electrical engineering from Stanford University. He is a Fellow of ACM and IEEE and a recipient of the 1998 IEEE Piore Award

Thursday, February 18, 2016, 3:30 pm - 5:00 pm
238 Broun Hall