The VLSI Design & Test Seminar Series
seeks to provide an open forum for various faculty, graduate and undergraduate students with research and development efforts in the area of design and test of VLSI systems, including application specific and programmable circuits in digital, analog, and mixed-signal microsystems. The goal is to promote further learning, discussion, and teamwork along with the conception and development of exciting new ideas.

The seminar series counts as a 1-credit course ELEC7950 (which may be repeated for up to 3 credits).

This seminar series sponsored by:

the Testing Group at Auburn:

Vishwani Agrawal - Design for Testability (DFT) and low-power design

Foster Dai - mixed-signal and analog design and testing

Vic Nelson - ASIC/FPGA testing and fault tolerance

Adit Singh - digital and mixed-signal VLSI design and Design for Testability (DFT)

Chuck Stroud - digital and mixed-signal Built-In Self-Test (BIST)

Fall 2007 schedule:

When: Wednesdays from 4-5:30pm

Where: Broun Hall room 235

Coordinator: Adit Singh

Invitation: If you are interested in presenting a seminar during Spring 2007, please contact the coordinator.

Notes: The following is a tentative schedule for Fall 2007. The link under Speaker is to an abstract of the presentation and the link under Topic is to a PDF file of the presentation slides.

Date	Speaker (w/ link to abstract)	Topic (w/ link to presentation slides after seminar date)
Aug. 22	Chuck Stroud	30 Years of Test Challenges and Solutions: How They Impact the Future
Aug. 29	Vishwani Agrawal	Using Hierarchy in Design Automation: The Fault Collapsing Problem
Sept. 5	Lee Lerner Bobby Dixon	Acoustic Emission Testing (AET) for Large Above Ground Storage Tanks: An IIT Madras and Auburn University Joint Case Study
Sept. 12	Gefu Xu	Flip-flop Selection to Maximize TDF Coverage with Partial Enhanced Scan
Sept. 19	Hillary Grimes	Delay Fault Simulation with Bounded Gate Delay Model
Sept. 26	Gefu Xu	Achieving High Transition Delay Fault Coverage with Partial DTSFF Scan Chains
Oct. 3	Victor P. Nelson	VLSI/FPGA Design and Test Flow with Mentor Graphics CAD Tools
Oct. 10	Vishwani Agrawal	Effectiveness Measures for VLSI Testing: Defective Parts per Million, Defect Coverage and Fault Coverage
Oct. 17	Fan Wang	Single Event Upsets: An Embedded Tutorial
Oct. 24	No Seminar	IEEE International Test Conf. week
Oct. 29	Dr. C. P. Ravikumar (Texas Instruments, Bangalore, India)	Power Infrastructure Aware Test Generation for System-on-Chip
Oct. 31	Gefu Xu	Delay Test Scan Flip-flop (DTSFF) Design and Its Applications for Scan Based Delay Testing (PhD Defense)
Nov. 7	Dr. Bruce Kim (Univ. of Alabama, Tuscaloosa)	Low Cost Automatic Mixed-Signal Board Test Using IEEE 1149.4
Nov. 14	Adit Singh	Process Variability and Defect Tolerance in Scaled CMOS: Methodology and Algorithms (Collaborative Research with Georgia Institute of Technology)
Nov. 28	Dr. Sule Ozev (Duke Univ.)	System-level and Circuit-level Test Approaches for State-of-the-art RF Transceivers
Dec. 5	Lee Lerner	Built-In Self-Test for Input/Output Tiles in Field Programmable Gate Arrays

Links to previous semesters of the VLSI Design & Test Seminar Series:

Spring 2007: Coordinator Chuck Stroud

Fall 2006: Coordinator Adit Singh

Spring 2006: Coordinator Vishwani Agrawal

Fall 2005: Coordinator Chuck Stroud

Spring 2005: Coordinator Adit Singh

Fall 2004: Coordinator Chuck Stroud