The VLSI Design & Test Seminar Series
seeks to provide an open forum for various faculty, graduate and undergraduate students with research and development efforts in the area of design and test of VLSI systems, including application specific and programmable circuits in digital, analog, and mixed-signal microsystems. The goal is to promote further learning, discussion, and teamwork along with the conception and development of exciting new ideas.

The seminar series counts as a 1-credit course ELEC7950 (which may be repeated for up to 3 credits).

This seminar series sponsored by:

the Testing Group at Auburn:

Vishwani Agrawal - Design for Testability (DFT) and low-power design

Foster Dai - mixed-signal and analog design and testing

Vic Nelson - ASIC/FPGA testing and fault tolerance

Adit Singh - digital and mixed-signal VLSI design and Design for Testability (DFT)

Chuck Stroud - digital and mixed-signal Built-In Self-Test (BIST)

Fall 2006 schedule:

When: Wednesdays from 4-5:30pm

Where: Broun Hall room 235

Coordinator: Dr. Adit Singh

Invitation: If you are interested in presenting a seminar during Fall 2006, please contact the coordinator.

Notes: The link under Speaker is to an abstract of the presentation and the link under Topic is to a PDF file of the presentation slides.

Date	Speaker (w/ link to abstract)	Topic (w/ link to presentation slides after seminar date)
Aug. 16	-	-
Aug. 23	Daniel Milton Lee Lerner	Embedded Processor-Based BIST for FPGAs & Fail-Silent and SEU Architectures for FPGAs An Architecture for Fail-Silent Operation of FPGAs and Configurable SoCs
Aug. 30	Adit D. Singh	Outlier Screening for "Zero" Defect IC Quality
Sept. 6	Charles Stroud	Testing Parity-Based Error Detection and Correction Circuits
Sept. 13	Vishwani D. Agrawal	Upper Bounding Fault Coverage in Stafan
Sept. 20	Gefu Xu	Delay Test Scan Flip-Flop: DFT for High Coverage Delay Testing
Sept. 27	Chris Erickson	An Overview of Serial ATA (SATA) Technology
Oct. 4	Kalyana R Kantipudi	A Reduced Complexity Algorithm for Minimizing N-Detect Tests
Oct. 11	Nitin Yogi	Spectral RTL Test Generation for Microprocessors
Oct. 18	Jins Alexander	Power Analysis and Estimation for Digital CMOS Circuits
Oct. 25	ITC Week
Nov. 1	Adit D. Singh	Design for Variability
Nov. 8	Khushboo Sheth Kyungseok Kim Fan Wang Siddharth Dantu	Low Power Architecture and Implementation of Multicore Design
Nov. 15	Victor P. Nelson	Mentor Graphics Simulation Tools for ASIC Design
Nov. 29	Kalyana R. Kantipudi (MS Thesis Defense)	Minimizing N-Detect Tests for Combinational Circuits
Dec. 6	Yuanlin Lu (PhD Thesis Proposal)	Power and Performance Optimization of Static CMOS Circuits with Process Variation

Links to previous semesters of the VLSI Design & Test Seminar Series:

Spring 2006: Coordinator Dr. Vishwani Agrawal

Fall 2005: Coordinator Dr. Chuck Stroud

Spring 2005: Coordinator Dr. Adit Singh

Fall 2004: Coordinator Dr. Chuck Stroud