Tuesday/Thursday, 11:00AM-12:15PM, Broun 235

Course Syllabus, Final Grades

FINAL EXAM (25%): May 6, 2006, 2:00-4:30PM, Broun 235, solution

The idea of a focused preparation is not to narrow down the scope of the course. The student remains responsible for all 18 chapters of the textbook and all 22 lectures. However, the following list is given to make the preparation for the final exam manageable. Questions will be based on:

1. Yield, fault coverage and defect level.

2. Stuck-at faults, fault equivalence, parallel fault simulation.

3. D-Algorithm and combinational ATPG.

4. Pseudorandom pattern generation for BIST.

5. Scan DFT, design rules, scan implementation.

Use of books, notes and a computer (not necessary) during the exam will be permitted.

Instructor: Professor Vishwani D. Agrawal, vagrawal@eng.auburn.edu, Broun 323, 334-844-1853.

Text book:

HOMEWORK (30%):

Homework 1 -- Problems 1.2 and 1.4, assigned 1/12/06, due 1/26/06, solution

Homework 2 -- Problems 3.2, 3.3 and 3.7, assigned 1/19/06, due 2/2/06, solution

Homework 3 -- Problems 4.7, 4.8 and 4.11, assigned 1/26/06, due 2/9/06, solution

Homework 4 -- Problems 5.8 and 5.16, assigned 2/2/06, due 2/16/06, solution

Homework 5 -- Problems 6.4 and 6.13, assigned 2/9/06, due 2/23/06, solution

Homework 6 -- Problems 7.4 and 7.14, assigned 2/16/06, due 3/2/06, solution

Homework 7 -- Derive the smallest test set to detect all faults of a four-bit ALU (netlist, schematic). You may use the Hitec/Proofs/Atalanta programs (user's manual, setup procedure) available on ECE computers. Document your procedure and results. Remember that known test sets of 12 vectors exist for this circuit. Assigned 2/23/06, due 3/9/06, Solution: for a 12-vector test set, see pages 50 and 63 of Doshi's master's thesis.

Homework 8 -- Problems 8.5 and 8.8, assigned 3/2/06, due 3/16/06, solution

Homework 9 -- Problems 9.13, 11.1 and 12.9, assigned 3/23/06, due 4/13/06, solution

Homework 10 -- Problems 13.1, 14.5, 14.6, 15.17 and 18.7, assigned 4/17/06, due 4/27/06 solution

RF Testing (SPECIAL ASSIGNMENT): Every student must attend the seminar talk on Wednesday, March 1, 2006, 4PM, Broun 235.

Before coming to the talk, please read the supplied document on RF testing.

PROJECT (25%), CLASS PRESENTATION (10%), TERM PAPER (10%), Project and Final Grades

Started 1/26/06, last update 3/23/06, completion as specified, next due dates: slides (specified below) and project report 4/27/06

CLASS PRESENTATION (Slides 5%, Talk 5%):

4/20/06 Alexander, Anbumony, Grimes

4/25/06 Hill, Milton, Qin

4/27/06 Sheth, Wang, White

Instructions: 1. Topic: Your class project accomplishments.

2. Duration: 20 minutes, including demo, if any.

3. Email 5-10 (including title and conclusion) slides at least one hour before the class. Talk time must not exceed 20 minutes.

Slide 1 -- Title

Slide 2 -- Problem statement

Slide 3 -- Background work, including most relevant references

Slides 4-5 -- Main ideas, analysis, algorithms

Slides 6-7 -- Results and inferences

Slide 8 -- Conclusion

TERM PAPERS AND PROJECT REPORTS:

Alexander: Paper (Statistical Fault Simulation) Report (Logic Simulation and Diagnosis)

Anbumony: Paper (Test Compaction) Report (Logic Simulation and Diagnosis)

Grimes: Paper (Concurrent Test Generation) Report (Logic Simulation and Diagnosis)

Hill: Paper (Transition Delay Faults) Report (Logic Simulation and Diagnosis)

Milton: Paper (Memory BIST for FPGAs) Report (Logic Simulation and Diagnosis)

Qin: Paper (Application-Specific FPGA Testing) Report (Logic Simulation and Diagnosis)

Sheth: Paper (Fault Diagnosis) Report (Logic Simulation and Diagnosis)

Wang: Paper (Random Access Scan) Report (Logic Simulation and Diagnosis)

White: Paper (Boundary Scan Standard) Report (Logic Simulation and Diagnosis)

LECTURES:

Lecture 0: Course Organization, 1/10/06

Lecture 1: Introduction, 1/10/06 (Chapter 1)

Lecture 2: VLSI Test Process and Equipment, 1/12/06 (Chapter 2)

Lecture 3: Test Economics, 1/17/06 (Chapter 3)

Lecture 4: Yield Analysis and Product Quality, 1/19/05 (Chapter 3)

Lecture 5: Fault Modeling, 1/24/06 (Chapter 4)

Lecture 6: Logic Simulation, 1/26/06 (Chapter 5)

Lecture 7: Fault Simulation, 1/31/06 and 2/2/06 (Chapter 5)

Lecture 8: Testability Measures, 2/7/06 and 2/9/06 (Chapter 6)

Lecture 9: Combinational ATPG, 2/14/06 and 2/16/06 (Chapter 7)

Lecture 10: Combinational ATPG and Logic Redundancy, 2/21/06 (Chapter 7)

Lecture 11: Advances in Combinational ATPG Algorithms, 2/23/06 (Chapter 7)

Lecture 12: Sequential Circuit ATPG -- Time-Frame Expansion, 2/28/06 and 3/2/06 (Chapter 8)

Lecture 13: Sequential Circuit ATPG -- Simulation-Based Methods, 3/7/06 and 3/9/06 (Chapter 8)

Lecture 14: Memory Test, 3/14/06 (Chapter 9)

Lecture 15: Memory NPSF and Parametric Test, 3/16/06 (Chapter 9)

Lecture 16: Analog Circuit Test, 3/21/06 (Chapters 10, 11 and 17)

Lecture 17: Delay Test, 3/23/06 and 4/4/06 (Chapter 12)

Lecture 18: IDDQ Testing, 4/6/06 (Chapter 13)

Lecture 19: Design for Testability (DFT) - Full Scan, 4/11/06 (Chapter 14)

Lecture 20: DFT - Partial, Random-Access and Boundary Scan, 4/11/06 Reading Assignment (Chapters 14 and 16)

Lecture 21: BIST - Built-In Self-Test, 4/13/06 (Chapter 15)

Lecture 22: System Test, 4/18/06 (Chapter 18)

PREVIOUS OFFERINGS BY PROF. V. AGRAWAL:

Spring 2005

Spring 2004: ELEC 7250 VLSI Testing, Class Assignments, Course Bulletin (Finals and Grades),