library ieee;
use ieee.std_logic_1164.all;

entity sramtest is
port ( clk, reset: in std_logic; 
	sw: in std_logic_vector(17 downto 0);
	addr: out std_logic_vector(17 downto 0);
	data : in std_logic_vector(15 downto 0);
	ce, oe, ub, lb, we: out std_logic;
     disp1, disp2, disp3, disp4 : out std_logic_vector(6 downto 0)); 
end sramtest;

architecture behavior of sramtest is

component hexto7seg1 is

port ( 	 hex_digit1 : in std_logic_vector(3 downto 0);
	 
		 segment1 :out std_logic_vector(6 downto 0)
	 );

end component hexto7seg1;

component hexto7seg2 is

port ( 	 hex_digit2 : in std_logic_vector(3 downto 0);
	 
		 segment2 :out std_logic_vector(6 downto 0)
	 );

end component hexto7seg2;

component hexto7seg3 is

port ( 	 hex_digit3 : in std_logic_vector(3 downto 0);
	 
		 segment3 :out std_logic_vector(6 downto 0)
	 );

end component hexto7seg3;

component hexto7seg4 is

port ( 	 hex_digit4 : in std_logic_vector(3 downto 0);
	 
		 segment4 :out std_logic_vector(6 downto 0)
	 );

end component hexto7seg4;

signal databus: std_logic_vector(15 downto 0);
signal display1, display2, display3, display4: std_logic_vector(6 downto 0);

begin

converter1: hexto7seg1 port map(databus(3 downto 0),display1);
converter2: hexto7seg2 port map(databus(7 downto 4),display2);
converter3: hexto7seg3 port map(databus(11 downto 8),display3);
converter4: hexto7seg4 port map(databus(15 downto 12),display4);

ce <= '0';
oe <= '0';
ub <= '0';
lb <= '0';
we <= '1';

process(clk, reset,sw)
begin
if reset='0' then

disp1 <= "1000000"; 
disp2 <= "1000000";
disp3 <= "1000000";
disp4 <= "1000000";

addr <= "000000000000000000";

elsif (clk='0' and clk'event) then

databus <= data;
addr(4 downto 0) <= sw(4 downto 0);
addr(17 downto 5)<= "0000000000000";
disp1 <= display1; 
disp2 <= display2;
disp3 <= display3;
disp4 <= display4;
end if;

end process;


end behavior;