library ieee; use ieee.std_logic_1164.all; use work.qsim_logic.all; entity trans is port( d : inout std_logic_vector(15 downto 0); a : out bit_vector(15 downto 0); b : in bit_vector(15 downto 0); rd,wr: in bit); end trans; architecture trans_arch of trans is begin process(rd,wr,d) begin if rd = '1' and wr = '0' then d<="ZZZZZZZZZZZZZZZZ"; a<= to_bitvector(d); elsif wr = '1' and rd = '0' then d <= to_stdlogicvector(b); else d<= "ZZZZZZZZZZZZZZZZ"; end if; end process; end trans_arch;