library ieee;
use ieee.std_logic_1164.all;
use work.qsim_logic.all;	     -- package with to_integer() function
use std.textio.all;                  -- For file operations

entity memory16 is
 port (dbus: inout std_logic_vector(15 downto 0);
       abus: in bit_vector(12 downto 0);
       mrd:   in bit;			-- active high read enable
       mwr:   in bit;			-- active high write enable
	 clk: in bit);
end memory16;

architecture reglevel of memory16 is
type mem is array(natural range <>) of std_logic_vector(15 downto 0);
signal M: mem(0 to 8191);

begin
  
 process (mrd,mwr,abus,dbus)
  variable init:    boolean := true;          -- true 1st time through
    begin

     -- Initialization of the memory
    if init then
	M <= (
		0 => "0000000000000000",
		1 => "0000000000000000",   
		2 => "0000000000000000",   
		3 => "0000000000000000",   
		4 => "0000000000000000",    
		5 => "0000000000000000",    
		6 => "0000000000000000",    
		7 => "0000000000000000",     
		8 => "0000000000000000",     
		9 => "0000000000000000",     
		10 => "0000000000000000",     
		others =>"0000000000000000"
              );
 	dbus <= "ZZZZZZZZZZZZZZZZ";
     init := false;                        -- Disable memory load
     end if;

   -- The actual memory read/write process
   if (mrd = '1') then   			-- read enabled
       dbus <= M(to_integer('0' & abus));	-- drive the bus
    elsif (mwr = '1') then   			-- write enabled
       dbus <= "ZZZZZZZZZZZZZZZZ";		-- disable drivers
       M(to_integer('0' & abus)) <= dbus;	-- write value
    else
       dbus<="ZZZZZZZZZZZZZZZZ";		--disable drivers
    end if;

  end process;

end;