ELEC 6730 - Microelectronic Fabrication
When and Where:
2001 Catalog Data: ELEC 6730. Microelectronic Fabrication (3) Lec. 2. Lab. 3. Pr., ELEC 2210 or departmental approval. Introduction to monolithic integrated circuit technology, bipolar and MOS processes and structures, elements of layout, design, fabrication and applications, experiments in microelectronic technologies.
Textbook: Introduction to Microelectronic Fabrication, R. C. Jaeger, Addison-Wesley, 1998.
Instructor: Y. Tzeng, Professor of ECE
Office: BN 412 (Tel: 844-1869;
email:
Goals: To develop an understanding of the basic processes used in fabrication of bipolar and MOS integrated circuits and to practice actual fabrication in the microelectronics laboratory
Prerequisites by topic:
1. Elementary understanding of bipolar junction transistors, field-effect transistors and electronic circuits
Topics:
1. Historical Overview
2. Introduction to Integrated Circuit Processing
§ Photolithography Process Dark Field/Light Field
§ Description of Basic NMOS Process
§ Description of Basic CMOS Process
§ Description of Basic Bipolar Process
3. Lithography
§ Clean Room/Wafer Cleaning
§ Photoresist Application Exposure Developing
§ Wet & Dry Etching
§ Mask Fabrication and Layout/Reduction/Step & Repeat
4. Thermal Oxidation
§ Reaction Kinetics
§ Derivation of FickĘs First Law
§ Linear and Parabolic Rate Constants
§ Oxidation Tables
5. Diffusion and Junction Formation
§ Substitutional /Interstitialcy /Interstitial
§ Derivation of FickĘs Second Law
§ Diffusion Coefficient/Segregation Coefficient/Solid Solubility
§ Erfc and Gaussian Diffusion Profiles
§ Formation of a pn junction/Irvin's curves
§ Successive diffusions
6. Process Characterization
§ Junction Depth Measurement via SIMS
§ Sheet Resistance/Resistor Layout
§ Van der Pauw Structures
§ Four-point probe
§ Oxide Thickness
7. Ion Implantation
§ Implant Dose/Energy
§ Projected Range/Straggle
§ Junction Formation
8. Thin Film Deposition
§ High Vacuum Systems
§ Electron Beam Evaporation/Sputtering
§ Chemical Vapor Deposition
§ Epitaxial Growth/Molecular Beam Epitaxy
9. Interconnect and Contacts
§ Metallization
§ Multilevel interconnect/CMP/Damescine Processes
§ Diffusion/Polysilicon/Silicides
§ Ohmic & Non-Ohmic Contacts
10. Packaging Technology
§ Die Attachment
§ Wirebonding
§ Dual in Line Package
§ PGA/LCC/Surface Mount/Flip-Chip/CSP
11. Yield
§ Defect Formation
§ Edge Dislocation
§ Stacking Faults
12. MOS Process Integration
13. Bipolar Process Integration
14. MEMS
15. Exams and Homework
16. Laboratory
Grades:
§ Two mid-term tests, each 20%
§ Homework 20%
§ Laboratory 20%
§ Final exam 20%
No credits for late homework. No make-up tests will be offered without written excuses approved by the instructor in advance.
Computer usage:
IC layout tools; SUPREME process simulator
Laboratory projects (including major items of equipment and instrumentation used):
An integrated circuit chip is designed, fabricated and tested by the students using the facilities of the microelectronics fabrication laboratory.
Students
who need special accommodations should make an appointment to discuss their
needs as soon as possible.