Solutions to Homework 9-2

(~04/30/2004)

9.77

(Note, Q1 and Q2 used in this circuit drawing are opposite to what are used in the textbook. You can use any number for Q as long as everything is consistent.)

1. When Q1 is off, V_C1=3 V

V_OH = V_CC = 3 V

2. When Q1 is driven into the saturation mode, V_C1 is small and between 0.04V and 0.3 V or so depending on how hard (how much base current) it is driven in to saturation. We will assume a reasonable value of 0.15 V for this case.

V_OL = V_CESAT = 0.15V

3. When the input voltage is low (logic zero), Q2 operates in the saturation mode with negligible collector current; therefore, Q2 is driven into deep saturation giving it a very small V_CE. In this case, we can reasonably assume a low-end value of V_CESAT = 0.04V for Q2.

If the input voltage rises, the voltage across the base and the emitter of Q1 will also rise while V_CESAT2 remains at 0.04V. When the input voltage rises so high that the base-emitter junction of Q1 becomes forward biased, that is V_{BE Q1} = 0.7 volts, Q1 starts to conduct causing the output voltage to fall from the supposedly 3 volts output voltage. The input voltage at this level is the maximum allowed input voltage, V_IL, which is given by

V_IL = 0.7 + ( - V_CESAT2 )= 0.7- 0.04 = 0.66V

4. When the input voltage is high (logic one), Q1 operates in the saturation mode with V_BESAT1 = 0.8V, and Q2 operates in the reserve active mode. For Q2, the base-collector junction is forward biased and the base-emitter junction is reserve biased.

If the input voltage decreases because of noises, the base emitter junction may get out of the reverse biased mode. When the base-emitter junction of Q2 becomes forward biased just like the base-collector junction of Q2, V_CE2 becomes zero. At this time, the input voltage is equal to V_BESAT1 =0.8 V. If the input voltage continues to decrease, Q2 will stop operating in the reverse active mode and Q1 will start to get out of the saturation mode. Therefore, this is the lowest allowed high input voltage, V_IH, that is acceptable as logic 1.

V_IH = V_BESAT1 = 0.8V

5. When the input voltage is high, i.e., V₁ = V_OH = 3 V

I_B2 = (V_CC – V_BC2 – V_BE1 )/ R₁ = (3 – 0.7 – 0.8) / 4K = 375uA

I_B1 = -I_C2 = (1+β_R ) x I_B2 = (1 + 0.25) x I_B2 = 469uA

The current flowing into the emitter of Q2 is equal to

I_IL = 469 – 375 uA = 94 uA

6. When the input voltage is low, i.e., V₁ = V_OL = 0.15V

The input voltage flowing out of the emitter of Q2 is given as (The negative value means that the current is flowing out of the emitter.)

I_IL = -(V_CC – V_BESAT2 – V₁)/R₁ = -( 3 – 0.8 – 0.15)/4K = -513uA

7. To find out the fanout when the low output voltage is connected to multiple inputs of the next logic gates:

I_CSAT1 = (3 – 0.15)/2K = 1.43 mA

The total current flowing through the collector of Q1 is the summation of I_CSAT1 and all the current flowing from the input terminal of the next logic gates. The ratio of the total collector current to the base current must be less than the beta (40) if Q1 is operating in the saturation mode.

That is, I_CSAT1 + N x (- I_IL ), where I_IL is a negative value, from input terminals of N logic gates connected to the collector of Q1 must be less than or equal to beta (40) times I_B1 in order for Q1 to be operating in the saturation mode.

1.43 + N(513uA) < = 40 x (469uA)

N < = 33.8 implies that the fan-out limit is N = 33

8. To find out the fanout limit when the output voltage is supposed to be high while Q1 is off and Q2 is operating in the RA mode:

The output voltage is equal to

5V- 2k x 93 uA x N,

that is equal to the V_CC minus the voltage drop across R₂. Although the current flowing into the collector of Q1 is zero, there is current flowing through R₂ into the input terminals of the next logic gates. Each logic gate with a high input voltage has been calculated to draw 93 uA.

In order for Q2 to operate in the RA mode, the input voltage can not be so low that V_BE2 becomes forward biased, i.e., V_BE2 must not become greater than 0.

Since high the output voltage is high (logic one)

V_B2 = V_BC2 + V_BE1 = 0.7 + 0.8 = 1.5 V

If the output voltage falls below 1.5 V, this output voltage can not guarantee to be treated as a logic one when used as the input voltage for the next logic gate.

Therefore, the maximum number of next logic gates, N, is limited to

5V- 2k x 93 uA x N > 1.5V

N < 3.5/2/0.093 = 18.8

Fanout N = 18 maximum.

9. The actual fanout limit is the lower number between 33 and 18.

The fanout is, therefore, N = 18.