Solutions to Homework Chapter 4-1

(Due: 03/03/2004)

4.4

a) T_ox = 50 nm

(For the second edition of the textbook, the thickness for this problem has been changed from 50 nm to 40 nm. Follow the same procedure shown below and use the thickness assigned in the textbook to work on this set of problems.)

b) b) T_ox = 20 nm

Using the result from a)

c) c) T_ox = 10 nm

Using the result from a)

4.15

a) For NMOS

 From Table 4.7,

 (b) Repeat the same procedure for (a).

4.22

Picking up two points from the graph in the saturation region,

For V_GS = 4 V, I_DS = 395uA

For V_GS = 3 V, I_DS = 140 uA

Therefore,

Taking ratios of these two equations

On solving the equation we get V_TN = 1.5 V >0.

This is an enhancement mode MOSFET.

Substituting value of V_TN = 1.5 V in any of the above equations gives

K_N = 125uA/V²

From Table 4.7,

Therefore,

W/L = 125/25 = 5/1

4.27

a) V_GS = 5 V V_TN = 1 V V_DS = 6 V

V_GS – V_TN = 5V – 1V = 4 V which is less than V_DS = 6V

Hence, saturation mode

b) V_GS = 0 V V_TN = 1 V V_DS = 6 V

Since V_GS is less than V_TN

Hence, cut off mode

c) V_GS = 2 V V_TN = 1 V V_DS = 2 V

V_GS – V_TN = 2V – 1V = 1 V which is less than V_DS = 2V

Hence, saturation mode.

d) V_GS = 1.5 V_TN = 1 V V_DS = 0.5 V

V_GS – V_TN = 1.5V – 1V = 0.5 V = V_DS

Hence, the MOS is on the boundary of linear mode and saturation mode.

e) The source and drain are interchanged in this transistor because negative V_DS. The Source is now used as the Darin and the Drain is now used as the Source. Let the Source terminal be grounded. Then, the gate voltage is 2.5 Volts and the real Source is at -0.5 volt. The actual voltage between the Gate and the real Source is 2.5-(-0.5) = 3 volts, which is greater than V_TN by 2 Volts. Since the voltage difference between the real Drain and the real Source is + 0.5 volts, which is less than 2 volts, the device is working in the linear mode.

V_GS – V_TN = (2.5 – (-0.5) – 1) = 2 V which is greater than V_DS = 0.5 V

f) The source and drain are interchanged in this case because of negative V_DS

Therefore, V_GS – V_TN = (3 – ( -6) – 1) = 8 V which is greater than V_DS = 6 V

Hence, linear mode