PUBLICATIONS by C. E. Stroud

* denotes graduate & undergraduate students directed by C. Stroud

Awards

1.         ACM/IEEE Design Automation Conf. Best Technical Paper Award in Design, Simulation, and Test category (1988): C. Stroud, An Automated Built-In Self-Test Approach for General Sequential Logic Synthesis

2.         IEEE Automatic Test Conf. Best Paper Award (2001): C. Stroud, J. Emmert, A. Taylor & T. Ferry*, Recovering Faulty Processing Elements to Enhance Reliability and Lifecycle in VLSI Processor Arrays

3.         IEEE North Atlantic Test Workshop Best Student Paper Honorable Mention (2007): B. Dixon* & C. Stroud, Analysis and Evaluation of Routing BIST Approaches for FPGAs

Books

1.         L.T. Wang, C. Stroud & N. Touba, System-on-Chip Test Architectures: Nanometer Design for Testability, Morgan Kaufmann, 2007

2.         C. Stroud, A Designer's Guide to Built-In Self-Test, Springer, 2002

3.         C. Stroud, Majority Voting Fault and Defect Tolerance in Very Large Scale and Wafer Scale Integrated Circuits, UMI, 1991

Book Chapters

1.         L.T. Wang & C. Stroud, Fundamentals of VLSI Testing, in Power-Aware Testing and Test Strategies for Low Power Devices, editors: P. Girard, N. Nicolici & X. Wen, Springer, 2009

2.         L.T. Wang, C. Stroud & K.T.Cheng, Logic Testing, in Encyclopedia of Computer Science and Engineering, editor: B. Wah, Wiley, 2009

3.         C. Stroud, L.T. Wang & Y.W. Chang, Introduction to Electronic Design Automation, in Electronic Design Automation: Synthesis, Verification, and Test, editors: L.T. Wang, Y.W. Chang & K.T.Cheng, Morgan Kaufmann, 2009

4.         L.T. Wang, C. Stroud & N. Touba, Introduction to SOC Testing, in System-On-Chip Test Architectures, editors: L.T. Wang, C. Stroud & N. Touba, Morgan Kaufmann, 2007

5.         C. Stroud, Field Programmable Gate Array Testing, in System-On-Chip Test Architectures, editors: L.T. Wang, C. Stroud & N. Touba, Morgan Kaufmann, 2007

6.         F. Dai & C. Stroud, Analog and Mixed-Signal Testing, in System-On-Chip Test Architectures, editors: L.T. Wang, C. Stroud & N. Touba, Morgan Kaufmann, 2007

7.         Y. Min & C. Stroud, Introduction to VLSI Testing, in VLSI Test Principles and Architectures, editors: L.T. Wang, C. Wu & X. Wen, Morgan Kaufmann, 2006

Sections in Book Chapters

1.         N. Touba & C. Stroud, Error Correction (in Chap 3: Fault Tolerant Design), in System-On-Chip Test Architectures, editors: L.T. Wang, C. Stroud & N. Touba, Morgan Kaufmann, 2007

2.         C. Stroud, FPGA Testing (in Chap 12: Test Technology Trends in the Nanometer Age), in VLSI Test Principles and Architectures, editors: L.T. Wang, C. Wu & X. Wen, Morgan Kaufmann, 2006

3.         C. Stroud, Device Level BIST Strategies (in Chap 3: BIST Strategies), in BIST At Your Fingertips Handbook, editor: V. Agrawal, AT&T, 1988

4.         C. Stroud, Case Studies I-IV (in Chap 4: BIST Case Studies), in BIST At Your Fingertips Handbook, editor: V. Agrawal, AT&T, 1988

Journal Papers

1.         Qin*, Cali, Dutton*, Starr*, Dai & Stroud, Selective Spectrum Analysis, IEEE Trans. on Industrial Electronics, Vol. 58, No. 10, 2011

2.         Dutton* & Stroud, On-Line Single Event Upset Detection and Correction in Field Programmable Gate Arrays, ISCA International J. on Computers & Their Applications, Vol. 17, No. 2, 2010

3.         Pulukuri* & Stroud, On Built-In Self-Test of Adders, J. Electronic Testing: Theory & Applications, Vol. 25, No. 6, 2009

4.         Qin*, Stroud & Dai, FPGA-Based Analog Functional Measurements for Adaptive Control in Mixed-Signal Systems, IEEE Trans. on Industrial Electronics, Vol. 54, No. 4, 2007

5.         Emmert, Stroud & Abramovici, On-Line Fault Tolerance for FPGA Logic Blocks, IEEE Trans. on VLSI Systems, Vol. 15, No. 2, 2007

6.         Smith, Xia & Stroud, An Automated BIST Architecture for Testing and Diagnosing FPGA Interconnect Faults, J. Electronic Testing: Theory & Applications, Vol. 22, No. 4, 2006

7.         Dai, Stroud & Yang, Automatic Linearity and Frequency Response Tests with Built-in Pattern Generator and Analyzer, IEEE Trans. VLSI Systems, Vol. 14, No. 6, 2006

8.         Abramovici, Stroud & Emmert, On-Line Built-In Self-Test and Diagnosis of FPGA Logic Resources, IEEE Trans. on VLSI Systems, Vol. 12, No. 12, 2004

9.         Abramovici & Stroud, BIST-Based Delay Fault Testing in FPGAs, J. Electronic Testing: Theory & Applications, Vol. 19, No. 5, 2003

10.     Abramovici & Stroud, BIST-Based Testing and Diagnosis of FPGA Logic Blocks, IEEE Trans. on VLSI Systems, Vol. 9, No. 1, 2001

11.     Stroud, Bailey* & Emmert, A New Method for Testing Re-programmable PLAs, J. Electronic Testing: Theory & Applications, Vol. 16, No. 6, 2000

12.     Heath, Ramamoorthy, Stroud & Hurt, Modeling, Design, and Performance Analysis of a Scalable Dynamic Load Balancing Circuit for a Parallel Data/Command Driven Architecture System, IEEE Trans. on Circuits and Systems, Vol. 44, No. 1, 1997

13.     Abramovici, Lee*, Stroud & Underwood*, Self-Test for FPGAs and CPLDs Requires No Overhead, Electronic Design, Nov., 1997

14.     Damarla, Stroud & Saythe, Multiple Error Detection and Identification via Signature Analysis, J. of Electronic Testing: Theory and Applications, Vol. 6, No. 6, 1995

15.     Stroud, Reliability of Majority Voting Based VLSI Fault Tolerant Circuits, IEEE Trans on VLSI Systems, Vol. 2, No. 4, 1994

16.     Crane, Davidson, Kane, Stroud & Wu, Trends in Digital Device Test Methodologies, AT&T Tech. J., Vol. 73, No. 2, 1994

17.     Stroud & Barbour, Testability and Test Generation for Majority Voting Fault-Tolerant Circuits, J. of Electronic Testing: Theory and Applications, Vol. 4, No. 3, 1993

18.     Gabara, Cyr & Stroud, Metastability in CMOS Master/Slave Flip-Flops, IEEE Trans. on Circuits & Systems, Vol. 39, No. 10, 1992

19.     Stroud, Automated Built-In Self-Test for Sequential Logic Synthesis, IEEE Design & Test of Computers, Vol. 5, No. 6, 1988

20.     Stroud, Munoz & Pierce, Behavioral Model Synthesis with CONES, IEEE Design & Test of Computers, Vol. 5, No. 3, 1988

21.     Jain & Stroud, Self-Testing of Embedded Memories, Nikkei Electronics, Vol. 4-20, No. 419, 1987

22.     Munoz & Stroud, Automatic Partitioning of Programmable Logic Devices, VLSI Systems Design, Vol. 3, No. 11, 1987

23.     Jain & Stroud, Self-Testing of Embedded Memories, IEEE Design & Test of Computers, Vol. 3, No. 5, 1986

24.     Todd, Stroud & Farrell, Identification of Nosean in Sodalite and Conversion of Nosean to Sodalite, Materials Research Bulletin, Vol. 15, 1980

25.     Stroud, Stencel & Todd, Infrared Spectra of Cathodochromic Sodalite, J. of Physical Chemistry, Vol. 83, No. 18, 1979

Patents

1.         Dai & Stroud, Automatic Analog Test and Compensation with Built-In Pattern Generator and Analyzer, US Pat. #7,428,683, 2008

2.         Stroud & Abramovici, Method for Delay-Fault Testing in Field Programmable Gate Arrays, US Pat. #7,412,343, 2008

3.         Abramovici, Emmert & Stroud, Fault Tolerant Operation of Field Programmable Gate Arrays, US Pat. #6,973,608, 2005

4.         Abramovici & Stroud, Identifying Faulty Programmable Interconnect Resources in Field Programmable Gate Arrays, US Pat. #6,966,020, 2005

5.         Abramovici, Emmert & Stroud, Fault Tolerant Operation of Reconfigurable Devices Using Adjustable System Clock, US Pat #6,874,108, 2005

6.         Abramovici & Stroud, On-Line Diagnosis of FPGA Logic Resources, US Pat #6,631,487, 2003

7.         Abramovici & Stroud, On-Line Built-In Self-Test of FPGA Interconnect Resources, US Pat #6,574,761, 2003

8.         Abramovici & Stroud, On-Line Built-In Self-Test of FPGA Logic Resources, US Pat #6,550,030, 2003

9.         Abramovici, Emmert & Stroud, Fault Tolerance via Incremental Reconfiguartion in FPGAs, US Pat #6,530,049, 2003

10.     Abramovici & Stroud, Fault Tolerant Operation of Field Programmable Gate Arrays, US Pat #6,256,758, 2001

11.     Abramovici, Stroud & Wijesuriya*, Method for Testing Field Programmable Gate Array Interconnect,US Pat #6,202,182, 2001

12.     Abramovici, Lee* & Stroud, Method for Testing & Diagnosing Field Programmable Gate Arrays, US Pat #6,108,806, 2000

13.     Kari, Stroud & Wu, Maintenance Register with Boundary Scan Interface, US Pat #6,052,808, 2000

14.     Stroud & Abramovici, Method & Apparatus for Testing Field Programmable Gate Arrays, US Pat #6,003,150, 1999

15.     Stroud & Abramovici, Method for Testing Field Programmable Gate Arrays, US Pat #5,991,907, 1999

16.     Canniff, Chao, Matten & Stroud, Digital Signal Processor Synchronous Network, US Pat #5,251,208, 1993

17.     Mozingo & Stroud, Built-In Self-Test Circuit, US Pat. # 5,280,000, 1993, European (DE, FR, GB, IT) Pat. #92303312.0, 1993

18.     Aadsen, Jain & Stroud, Integrated Circuit with Memory Self-Test, US Pat. #4,872,168, 1989, CA Pat. #1,299,289, 1992

Conference Papers

1.         Lusco*, Dailey* & Stroud, Built-In Self-Test for Multipliers in Altera Cyclone II Field Programmable Gate Arrays, Proc. Southeastern Symp. on System Theory, 2011

2.         Dailey*, Garrison*, Pulukuri* & Stroud, Built-In Self-Test of Embedded Memory Cores in Virtex-5 Field Programmable Gate Arrays, Proc. Southeastern Symp. on System Theory, 2011

3.         Stroud & Da Cunha*, Built-In Self-Test of Programmable Clock Buffers in Virtex-4, Virtex-5 and Virtex-6 FPGAs, Proc. Southeastern Symp. on System Theory, 2011

4.         Stroud & Dutton*, The First Clock Cycle is a Real BIST, Proc. International Conf. on Embedded Systems and Applications, 2010

5.         Dutton* & Stroud, Soft-Core Embedded Processor-Based Built-In Self-Test of FPGAs: A Case Study, Proc. IEEE Southeast Symp. on System Theory, 2010

6.         Dutton*, Lerner*, Vemula* & Stroud, On System-Level Use of BIST for Programmable Input/Output Buffers in FPGAs, Proc. IEEE Southeast Regional Conf, 2010

7.         Pulukuri*, Starr* & Stroud, On Built-In Self-Test of Multipliers, Proc. IEEE Southeast Regional Conf, 2010

8.         Lusco* & Stroud, PSIM: A Processor SIMulator for Basic Computer Architecture and Operation Education, Proc. IEEE Southeast Regional Conf, 2010

9.         Dutton* & Stroud, Soft Core Embedded Processor Based Built-In Self-Test of FPGAs, Proc. IEEE International Symp. on Defect and Fault Tolerance in VLSI Systems, 2009

10.     Starr*, Qin*, Dutton*, Stroud, Dai & Nelson, Automated Generation of BIST and Measurement Circuitry for Mixed-Signal Circuits and Systems, Proc. IEEE International Symp. on Defect and Fault Tolerance in VLSI Systems, 2009

11.     Starr*, Wersinger, Chapman, Riggs, Nelson, Klingelhoeffer & Stroud, Application of Embedded Systems in Low Earth Orbit for Measurement of Ionospheric Anomalies, Proc. International Conf. on Embedded Systems and Applications, 2009

12.     Dutton*, Ali*, Stroud & Sunwoo*, Embedded Processor Based Fault Injection and SEU Emulation for FPGAs, Proc. International Conf. on Embedded Systems and Applications, 2009

13.     Dutton* & Stroud, Built-in Self-test of Embedded SEU Detection and Correction Cores in Virtex-4 and Virtex-5 FPGAs, Proc. International Conf. on Embedded Systems and Applications, 2009

14.     Garrison*, Milton* & Stroud, Built-In Self-Test of Embedded Programmable Memory Resources in Virtex-4 FPGAs, Proc. ISCA International Conf. on Computers and Their Applications, 2009

15.     Dutton* & Stroud, Single Event Upset Detection and Correction in Virtex-4 and Virtex-5 FPGAs, Proc. ISCA International Conf. on Computers and Their Applications, 2009

16.     Dutton* & Stroud, Built-In Self-Test of Configurable Logic Blocks in Virtex-5 FPGAs, Proc. IEEE Southeastern Symp. on System Theory, 2009

17.     Dutton* & Stroud, Built-In Self-Test of Programmable Input/Output Tiles in Virtex-5 FPGAs, Proc. IEEE Southeastern Symp. on System Theory, 2009

18.     Pulukuri* & Stroud, Built-In Self-Test of Digital Signal Processors in Virtex-4 FPGAs, Proc. IEEE Southeastern Symp. on System Theory, 2009

19.     Yao*, Dixon*, Stroud & Nelson, Built-In Self-Test of Programmable Interconnect in Virtex-4 FPGAs, Proc. IEEE Southeastern Symp. on System Theory, 2009

20.     Qin*, Stroud & Dai, Test Time of Multiplier/Accumulator Based Output Response Analyzer in Built-In Analog Functional Testing, Proc. IEEE Southeastern Symp. on System Theory, 2009

21.     Yao*, Dixon*, Stroud & Nelson, Built-In Self-Test of Global Routing Resources in Virtex-4 FPGAs, Proc. IEEE North Atlantic Test Worshop, 2008

22.     Dutton*, Lerner* & Stroud, Built-In Self-Test of Programmable I/O Cells in Virtex-4 FPGAs, Proc. IEEE North Atlantic Test Worshop, 2008

23.     Qin*, Stroud & Dai, Noise Figure Measurement Using Mixed-Signal BIST, Proc. IEEE International Symp. on Circuits and Systems, 2007

24.     Dixon* & Stroud, Analysis and Evaluation of Routing BIST Approaches for FPGAs, Proc. IEEE North Atlantic Test Worshop, 2007 (received Honorable Mention for Best Student Paper Award)

25.     Qin*, Stroud & Dai, Phase Delay Measurement and Calibration in Built-In Analog Functional Testing, Proc. IEEE Southeastern Symp. on System Theory, 2007

26.     Milton*, Dhingra* & Stroud, Embedded Processor Based Built-In Self-Test and Diagnosis of Logic and Memory Resources in FPGAs, Proc. International Conf. on Embedded Systems and Applications, 2006

27.     Lerner* & Stroud, An Architecture for Fail-Silent Operation of FPGAs and Configurable SoCs, Proc. International Conf. on Embedded Systems and Applications, 2006

28.     Qin*, Stroud & Dai, Phase Delay in MAC-based Analog Functional Testing in Mixed-Signal Systems, Proc. IEEE North Atlantic Test Workshop, 2006

29.     Dhingra*, Milton* & Stroud, BIST of Logic and Memory Resources in Virtex-4 FPGAs, Proc. IEEE North Atlantic Test Workshop, 2006

30.     Lerner*, Vemula* & Stroud, System-Level BIST for Programmable I/O Buffers in FPGAs and SoCs, Proc. IEEE North Atlantic Test Workshop, 2006

31.     Smith, Xia & Stroud, A BIST Approach for Detection and Diagnosis of  FPGA Interconnect Faults, Proc. IEEE North Atlantic Test Workshop, 2006

32.     Stroud, Yang & Dai, Analog Frequency Response Measurements in Mixed-Signal Systems, Proc. IEEE International Symp. on Circuits and Systems, 2006

33.     Vemula* & Stroud, Built-In Self-Test of Programmable I/O Buffers in FPGAs and SoCs, Proc. IEEE Southeastern Symp. on System Theory, 2006

34.     Sunwoo* & Stroud, Built-In Self-Test of Configurable Cores in SoCs Using Embedded Processor Dynamic Reconfiguration, Proc. International SoC Design Conf., 2005

35.     Stroud & Garimella*, Built-In Self-Test and Diagnosis of Multiple Embedded Cores in SoCs, Proc. International Conf. on Embedded Systems and Applications, 2005

36.     Yang, Dai & Stroud, Built-In Self-Test for Automatic Analog Frequency Response Measurement, Proc. IEEE International Symp. on Circuits and Systems, 2005

37.     Sankaranarayanan* & Stroud, Built-In Self-Test for a Monobit Fast Fourier Transform Receiver, Proc. IEEE North Atlantic Test Workshop, 2005

38.     Vemula* & Stroud, Built-In Self-Test of I/O Buffers in Atmel FPGAs,” Proc. IEEE North Atlantic Test Workshop, 2005

39.     Sunwoo*, Garimella* & Stroud, On Embedded Processor Reconfiguration of Logic BIST for FPGA Cores in SoCs, Proc. IEEE North Atlantic Test Workshop, 2005

40.     Dhingra*, Garimella*, Newalkar* & Stroud, Built-In Self-Test for Virtex and Spartan II FPGAs Using Partial Reconfiguration, Proc. IEEE North Atlantic Test Workshop, 2005

41.     Stroud, Garimella* & Sunwoo*, On-Chip BIST-Based Diagnosis of Embedded Programmable Logic Cores in System-on-Chip Devices, Proc. ISCA International Conf. on Computers and Their Applications, 2005

42.     Garimella* & Stroud, A System for Automated Built-In Self-Test of Embedded Memory Cores in System-on-Chip, Proc. IEEE Southeastern Symp. on System Theory, 2005

43.     Stroud, Sunwoo*, Garimella* & Harris*, Built-In Self-Test for System-on-Chip: A Case Study, Proc. IEEE International Test Conf., 2004

44.     Dai, Stroud, Qi & Yang, Automatic Linearity (IP3) Test with Built-in Pattern Generator and Analyzer, Proc. IEEE International Test Conf., 2004

45.     Stroud, Harris*, Garimella* & Sunwoo*, Built-In Self-Test Configurations for Atmel FPGAs Using Macro Generation Language, Proc. IEEE North Atlantic Test Workshop, 2004

46.     Stroud, Morton* & Islam*, An Automated BIST Approach for Mixed-Signal Systems, Proc. IEEE North Atlantic Test Workshop, 2004

47.     Qi, Dai, Stroud & Yang, Analog Circuit Testing Using Built-In Direct-Digital Synthesis, Proc. IEEE North Atlantic Test Workshop, 2004

48.     Stroud, Making It Real: Complex Specification-Based Projects for VLSI, VHDL, and Capstone Design, Proc. ASEE Southeast Annual Conf., 2004

49.     Stroud, Leach* & Slaughter*, BIST for Xilinx 4000 and Spartan Series FPGAs: a Case Study, Proc. IEEE International Test Conf., 2003

50.     Stroud, Morton*, Islam* & Alassaly*, A Mixed-Signal BIST Approach for Analog Circuits, Proc. IEEE Southest Symp. on Mixed-Signal Design, 2003

51.     Slaughter* & Stroud, Fault Injection Emulation in Field Programmable Analog Arrays, Proc. IEEE Southest Symp. on Mixed-Signal Design, 2003

52.     Stroud, Nall*, Lashinsky* & Abramovici, BIST-Based Diagnosis of FPGA Interconnect, Proc. IEEE International Test Conf,, 2002

53.     Abramovici, Stroud & Emmert, Using Embedded FPGAs for SoC Yield Enhancement, Proc. ACM/IEEE Design Automation Conf., 2002

54.     Abramovici & Stroud, BIST-Based Delay Fault Testing in FPGAs, Proc. IEEE International On-Line Testing Symp., 2002

55.     Stroud, Nall*, Taylor*, Ford* & Charnley, A System for Automated Generation of Built-In Self-Test for FPGAs, Proc. International Conf. on System Engineering, 2002

56.     Bailey* & Stroud, Embedded Logic Analyzer for On-Line System Analysis, Proc. International Conf. on Information Systems Analysis and Synthesis, 2002 (received Best Paper Award)

57.     Stroud, Lashinsky*, Nall*, Emmert & Abramovici, On-Line BIST and Diagnosis of FPGA Interconnect Using Roving STARs, Proc. IEEE International On-Line Testing Symp, 2001

58.     Emmert, Stroud, Baumgart, Kataria & Abramovici, On-Line Fault-Tolerance for FPGA Interconnect via Incremental Reconfiguration, Proc. IEEE International Symp. on Defect and Fault Tolerance in VLSI Systems, 2001

59.     Slaughter*, Stroud, Emmert & Skaggs, Fault Injection Emulation for Field Programmable Gate Arrays, Proc. ITCOM, 2001

60.     Stroud, Emmert, Taylor & Ferry*, Recovering Faulty Processing Elements to Enhance Reliability & Lifecycle in VLSI Processor Arrays, Proc. IEEE Automatic Test Conf., 2001 (received Best Paper Award)

61.     Heath, Vocke*, Stroud & Emmert, Routing Algorithms for Complex Programmable Logic Device Manufacturing Test Development, Proc. IEEE Automatic Test Conf. 2001

62.     Abramovici, Emmert & Stroud, Roving STARs: An Intrgrated Approach to On-Line Testing, Diagnosis, and Fault Tolerance for FPGAs in Adaptive Computing Systems, Proc. IEEE Evolvable Hardware Conf., 2001

63.     Stroud, Bailey*, Emmert, Nickolic & Chhor, Bridging Fault Extraction from Physical Design Data for Manufacturing Test Development, Proc. IEEE International Test Conf., 2000

64.     Abramovici & Stroud, Improved BIST-Based Diagnosis of FPGA Logic Blocks, Proc. IEEE International Test Conf., 2000

65.     Emmert, Stroud, Cheatham, Taylor*, Kataria & Abramovici, Predicting Performance Penalty for fault Tolerance in Roving Self-Testing AReas (STARs), Proc. International Conf. on Field Programmable Logic, 2000

66.     Stroud, Emmert & Bailey*, A New Bridging Fault Model for More Accurate Fault Behavior, Proc. IEEE Automatic Test Conf., 2000

67.     Bailey*, Stroud, Chhor, Lau & Orso, A Method for Testing Partially Programmable Logic Arrays in CPLDs, Proc. IEEE Automatic Test Conf., 2000

68.     Abramovici, Stroud, Skaggs* & Emmert, Improving BIST-Based Diagnosis for Roving STARs, Proc. IEEE International On-Line Testing Symp, 2000

69.     Emmert, Stroud, Skaggs* & Abramovici, Dynamic Fault Tolerance in FGPAs via Partial Reconfiguration, Proc. Field Programmable Custom Computing Machines Conf., 2000

70.     Vocke*, Stroud, Heath, Chhor & Orso, Computer Aided Routing for Complex Programmable Logic Device Manufacturing Test Development, Proc. IEEE Southeast Regional Conf., 2000

71.     Abramovici, Stroud, Hamilton*, Wijesuriya* & Verma, Using Roving STARs for On-Line Testing and Diagnosis of FPGAs for Fault Tolerant Applications, Proc. IEEE International Test Conf., 1999

72.     Hamilton*, Gibson*, Wijesuriya* & Stroud, Enhanced BIST-Based Diagnosis of FPGA via Boundary Scan Access, Proc. IEEE VLSI Test Symp., 1999 (nominated for Best Student Paper Award)

73.     Heath, Stroud & Leong, Development of a Test Environment for Pre- and Post-Synthesis Verification of Correct VHDL Description of Core Processor Systems, Proc. VHDL International User’s Forum, 1999

74.     Heath, Stroud, Leong & Damarla, Procedures for the Development of Legacy Processor Systems and a Procedure Verifying Case-Study Example, Proc. IEEE International Application Specific Integrated Circuits Conf., 1999

75.     Stroud, Yield Modeling for Majority Voting Based Defect-Tolerant VLSI Circuits, Proc. IEEE Southeast Regional Conf., 1999

76.     Hamilton*, Wijesuriya*, Gibson* & Stroud, Methods for Boundary Scan Access of Built-In Self-Test for Field Programmable Gate Arrays, Proc. IEEE Southeast Regional Conf., 1999 (nominated for Best Student Paper Award)

77.     Kondagunturi, Bradley, Magard* & Stroud, Benchmark Circuits for Analog and Mixed-Signal Testing, Proc. IEEE Southeast Regional Conf., 1999

78.     Lewis*, Lim*, Puckett* & Stroud, A Prototype Unit for Built-In Self-Test of Analog Circuits, Proc. IEEE Southeast Regional Conf., 1999

79.     Maggard* & Stroud, Built-In Self-Test for Analog Circuits in Mixed-Signal Systems, Proc. IEEE Southeast Regional Conf., 1999

80.     Abramovici, Stroud, Hamilton*, Wijesuriya* & Verma, On-Line Testing and Diagnosis of FPGAs with Roving STARs, Proc. IEEE International On-Line Testing Symp., 1999

81.     Stroud, Wijesuriya*, Hamilton* & Abramovici, Built-In Self-Test of FPGA Interconnect, Proc. IEEE International Test Conf., 1998

82.     Westerman*, Stroud, Heath & Kumar, Delay Fault Analysis Using Discrete Event System Approach, Proc. IEEE Automatic Test Conf., 1998

83.     Stroud & Tannehill*, Applying Built-In Self-Test to Majority Voting Fault Tolerant Circuits, Proc. IEEE VLSI Test Symp., 1998

84.     Westerman*, Kumar, Stroud & Heath, Discrete Event System Approach for Delay Fault Analysis in Digital Circuits, Proc. American Control Conf., 1998

85.     Karri, Wu, Stroud & Ding*, Parameterized VHDL Library for On-Line Testing, Proc. Lucent Technologies Electronic Testing Conf., 1998

86.     Stroud, Wijesuriya*, Hamilton* & Abramovici, Built-In Self-Test of FPGA Interconnect, Proc. IEEE International On-Line Testing Symp., 1998

87.     Stroud, Ding*, Long*, Yang*, Karri & Wu, Maximizing the Effectiveness of On-Line Testing Functions, Proc. IEEE International On-Line Testing Symp., 1998

88.     Stroud, Lee* & Abramovici, BIST-Based Diagnostics for FPGA Logic Blocks, Proc. IEEE International Test Conf., 1997

89.     Stroud, Ding*, Seshadri*, Kim, Roy, Karri & Wu, A Parameterized VHDL Library for On-Line Testing, Proc. IEEE International Test Conf., 1997

90.     Gibson*, Gray* & Stroud, Boundary Scan Access to BIST for Field Programmable Gate Arrays, Proc. IEEE International Application Specific Integrated Circuits Conf., 1997

91.     Stroud, Karunaratna* & Bradley, Digital Components for Built-In Self-Test of Analog Circuits, Proc. IEEE International Application Specific Integrated Circuits Conf., 1997

92.     Westerman*, Stroud & Heath, Delay Fault Modeling and Testability Analysis Using Temporal Logic, Proc. IEEE Automatic Test Conf., 1997

93.     Abramovici, Lee* & Stroud, BIST-Based Diagnostics for FPGA Logic Blocks, Proc. IEEE International On-Line Testing Symp.1997

94.     Abramovici & Stroud, Iterative Logic Array Based BIST for FPGAs, Proc. IEEE International On-Line Testing Symp., 1996

95.     Stroud & Damarla, Efficient Error Bit Identification from Failing Signatures, Proc. IEEE International Application Specific Integrated Circuits Conf., 1996

96.     Damarla, Stroud & Michael, A New Approach to Boolean Function Minimization, Proc. IEEE International Application Specific Integrated Circuits Conf., 1996

97.     Tungate*, He*, Seshadri* Stroud, Sullivan*, & Damarla, Design Automation Tools for Built-In Self-Test Implementations, Proc. IEEE Automatic Test Conf., 1996

98.     Stroud, Lee*, Konala* & Abramovici, Using ILA Testing for BIST in FPGAs, Proc. IEEE International Test Conf., 1996

99.     Stroud, He* & Damarla, Register Size vs. Fault Coverage in Modified Circular Built-In Self-Test, Proc. IEEE Automatic Test Conf., 1996

100. Stroud, Lee*, Konala* & Abramovici, Selecting Built-In Self-Test Configurations for Field Programmable Gate Arrays, Proc. IEEE Automatic Test Conf., 1996

101. Stroud, Konala*, Chen* & Abramovici, Built-In Self-Test for Field Programmable Gate Array Logic Blocks, Proc. IEEE VLSI Test Symp., 1996

102. Damarla & Stroud, Design of Signature Registers for Double Bit Error Identification, Proc. International Symp. on Circuits and Systems, 1996

103. Damarla, Stroud, Tungate*, Keyes & Michael, Improving the Effectiveness of Circular BIST, Tech. Digest Government Microelectronics Applications Conf, 1996

104. Stroud, Chen*, Konala* & Abramovici, Evaluation of FPGA Resources for BIST of Programmable Logic Blocks, Proc. ACM International Symp. on FPGAs, 1996

105. Damarla, Su, Chung, Stroud & Michael, A Built-In Self-Test Scheme for VLSI, Proc. Asia and Pacific Design Automation Conf., 1995

106. Fields* & Stroud, A Test Machine for Digital VLSI Circuits Fabricated Through MOSIS, Proc. IEEE Automatic Test Conf., 1995

107. Sullivan* & Stroud, Reducing the Cost of Circular Built-In Self-Test by Selective Flip-Flop Replacement, Proc. IEEE Automatic Test Conf., 1995 (nominated for Best Student Paper Award)

108. Russ* & Stroud, Non-Intrusive Built-In Self-Test for FPGA and MCM Applications, Proc. IEEE Automatic Test Conf., 1995

109. Das* & Stroud, A Multiple Fan-out Static Routing Scheme for Field Programmable Printed Circuit Boards, Proc. IEEE International Application Specific Integrated Circuits Conf., 1995

110. Stroud & Ryan, Multiple Fault Simulation with Random and Cluster Fault Injection Capabilities, Proc. IEEE International Application Specific Integrated Circuits Conf., 1995

111. Stroud & Damarla, Improving the Efficiency of Error Identification via Signature Analysis, Proc. IEEE VLSI Test Symp., 1995

112. Abramovici, Chen* & Stroud, Finally, A Free Lunch: BIST (for FPGAs) Without Overhead!, Proc. AT&T Conf. on Electronic Testing, 1995

113. Abramovici & Stroud, No Overhead Built-In Self-Test for FPGAs, Proc. IEEE International On-Line Testing Symp., 1995

114. Stroud & Ericson, Computer-Aided Design-Verification Vector Generation, Proc. IEEE International Application Specific Integrated Circuits Conf., 1994

115. Stroud & Liang, Design Verification Techniques for System Level Testing Using ASIC Level BIST Implementations, Proc. IEEE International Application Specific Integrated Circuits Conf., 1993

116. Stroud, Problems Associated with the Hardware Implementation of Software Algorithms Using Behavioral Model Synthesis, Proc. ACM/IEEE International Workshop on Hardware-Software Co-Design, 1992

117. Stroud & Shaw, An ASIC Level Built-In Self-Test Implementation for System Level Testing, Proc IEEE International Application Specific Integrated Circuits Conf., 1991

118. Stroud, Built-In Self-Test for High-Speed Data-Path Circuitry, Proc. IEEE International Test Conf., 1991

119. Stroud, Distractions in Design for Testability and Built-In Self-Test, Proc. IEEE International Test Conf., 1991

120. Gabara, Cyr, & Stroud, Metastability in CMOS Master/Slave Latches, Proc. IEEE Custom Integrated Circuits Conf., 1991

121. Thompson, Gabara & Stroud, A 180 MHz ASIC for High-Speed Interfaces, Proc. IEEE International Solid- State Circuits Conf., 1991

122. Stroud & Barbour, Parallel Processing and Hardware Acceleration for Synthesis of VLSI Devices from Behavioral Models, Proc. International Conf. on Parallel Processing, 1990

123. Stroud & Barbour, Reliability, Testability, and Yield of Majority Voting VLSI, Proc. IEEE International Application Specific Integrated Circuits Conf., 1990

124. Stroud, BIST for High-Speed Self-Routing Networks, Proc. AT&T Conf. on Electronic Testing, 1990

125. Stroud & Barbour, Design for Testability and Test Generation for Static Redundancy System Level Fault Tolerant Networks, Proc. IEEE International Test Conf., 1989

126. Pradhan, Stroud & Tulloss, An Automated Built-In Self-Test and Partial Scan Testing Methodology, Proc. AT&T Conf. on Electronic Testing, 1988

127. Pierce & Stroud, A Highly Automated Design System for Rapid Product Development from Architecture to ASICs, Proc. IEEE Custom Integrated Circuits Conf., 1988

128. Stroud, An Automated Built-In Self-Test Approach for General Sequential Logic Synthesis, Proc. ACM/IEEE Design Automation Conf., 1988 (received Best Technical Paper Award)

129. Stroud, A BIST Approach for Automated Logic Synthesis, Proc. AT&T Conf. on Electronic Testing, 1987

130. Stroud & Cyr, Built-In Self-Test for Embedded RAMs, ROMs, and PLAs, in Custom VLSI, Proc. National Communication Forum, 1986

131. Stroud, Munoz & Pierce, Automated Synthesis of Programmable Logic and VLSI from Behavioral Models, Proc. National Communication Forum, 1986

132. Pierce & Stroud, Impact of Behavioral Modeling and Synthesis on the Design Process, Proc. National Communication Forum, 1986

133. Stroud, Munoz & Pierce, CONES: A System for Automated Synthesis of VLSI and Programmable Logic from Behavioral Models, Proc. IEEE International Conf. on Computer-Aided Design, 1986

134. Stroud, A BIST Circuit for Embedded RAMs, ROMs, and PLAs, in VLSI Devices, Proc. AT&T Conf. on Electronic Testing, 1985

Workshop and Poster Presentations

1.         Lusco*. Dailey* & Stroud, A Built In Self Test Approach for Altera Multipliers, Auburn University Undergraduate Research and Creative Scholarship Forum, 2010

2.         Tomas* & Stroud, Fault Simulation of Embedded Multiplier Built-In Self-Test, Auburn University Undergraduate Research and Creative Scholarship Forum, 2010

3.         Stroud, System Level Testing of Field Programmable Gate Arrays, Auburn University Huntsville Wireless Research Reception, 2008

4.         Qin*, Dai & Stroud, System Level Test and Measurement of Mixed-Signal and RF Circuitry, Auburn University Huntsville Wireless Research Reception, 2008

5.         Qin*, Stroud & Dai, DDS-Based Mixed-Signal Built-In Self-Test (BIST) System, Vodafone Fellows Initiative Symp., 2007

6.         Stroud, Kondagunturi, Magard* & Bradley, Benchmark Circuits for Analog and Mixed-Signal Testing, Southeastern Workshop on Mixed-Signal VLSI, 1999

7.         Maggard* & Stroud, Built-In Self-Test for Analog Circuits in Mixed-Signal Systems, Southeastern Workshop on Mixed-Signal VLSI, 1999

8.         Stroud, Karunaratna*, Maggard* & Bradley, Mixed Signal Based Built-In Self-Test for Analog Circuits, Southeastern Workshop on Mixed-Signal VLSI and Monolithic Sensors, 1998

9.         He*, Stroud & Damarla, Modified Circular Built-In Self-Test for VLSI Devices, International Soc. of Hybrid Microelectronics Regional Conf., 1996

10.     Tungate*, He*, Seshadri*, Stroud & Damarla, Automated Synthesis of Built-In Self-Test in VLSI, International Soc. of Hybrid Microelectronics Regional Conf., 1996

11.     Lee*, Stroud & Abramovici, Built-In Self-Test for Field Programmable Gate Arrays, International Soc. of Hybrid Microelectronics Regional Conf., 1996

12.     Gibson*, Gray* & Stroud, Design of an ASIC for BIST in FPGAs, International Soc. of Hybrid Microelectronics Regional Conf., 1996

13.     Stroud, Applying BIST to Majority Voting Based Fault-Tolerant Circuits, IEEE Built-In Self-Test Workshop, 1992

14.     Stroud, BIST for High-Speed Self-Routing Networks, IEEE Built-In Self-Test Workshop, 1991

15.     Stroud & Barbour, Testability of Gate-Level Fault-Tolerant Circuits, AT&T Symp. on Fault Tolerance, 1988

16.     Munoz & Stroud, LSLgen: A Tool for Automatic Logic Simulation Language Generation, AT&T Symp. on Computer-Aided Enegineering and Design, 1988

17.     Stroud & Pierce, A Simulation Environment for Evaluation of Concurrent Checking Circuitry, IEEE Design for Testability Workshop, 1987

18.     Stroud, A BIST Approach for Automated Logic Synthesis, IEEE Built-In Self-Test Workshop, 1987

19.     Stroud & Pierce, A Simulation Environment for Evaluation of Concurrent Checking Circuitry, AT&T Design for Manufacturability Conf., 1987

20.     Stroud & Munoz, A Unit Level BIST Application for System Level Diagnostics, IEEE Built-In Self-Test Workshop, 1986

21.     Stroud & Kalvonjian, A Complete Application of Built-In Self-Test at the Device Level, AT&T Symp. on Fault Tolerance, 1986

22.     Stroud & Munoz, A Unit Level BIST Application for System Level Diagnostics, IEEE Built-In Self-Test Workshop, 1986

23.     Stroud, A BIST Circuit for Embedded RAMs, ROMs, and PLAs, in VLSI Devices, IEEE Built-In Self-Test Workshop, 1985

24.     Stroud, Stencel, & Todd, Infrared and Raman Spectra of Cathodochromic Sodalite, Symp. on Molecular Spectroscopy, 1977

Invited Presentations by C. Stroud

1.         BAE Systems, Built-In Self-Test for FPGAs, May 2009

2.         IEEE International Test Conf., FPGAs: Excellent Platforms for SoC Testing R&D, Oct. 2008

3.         Altera Corp., Production System-Level Use of Built-In Self-Test for FPGAs, Oct. 2008

4.         Altera Corp., Fail Safe Design Assurance for FPGAs, Oct. 2008

5.         Cypress International Technical Conf. Keynote Address, Thirty Years of Test Challenges and Solutions: How They Impact the Future, July 2007

6.         Xilinx Inc., Current AUBIST Research and Development for FPGAs, May 2007

7.         Xilinx Inc., Embedded Processor-Based Built-In Self-Test for FPGAs, Feb. 2006

8.         AdTran Inc., Huntsville, AL, Current Research and Development in Built-In Self-Test, Nov. 2005

9.         IBM VLSI Test Seminar Series, FPGA Test and Diagnosis, Sept. 2005

10.     Select Univ. Technologies Inc., On-Chip Automatic Analog Functional Testing and Measurements, May 2005

11.     Warner-Robbins ABF, Built-In Self-Test, Diagnosis, and Fault-Tolerance in FPGAs, May 2004

12.     Alabama Microelectronics Science & Technology Seminar Series, Built-In Self-Test: Making Chips Test and Diagnose Themselves, Apr. 2004

13.     IEEE Montgomery-Auburn Section Meeting, Built-In Self-Test for FPGAs, Feb. 2004

14.     Duke Univ., Built-In Self-Test for FPGAs and Mixed-Signal Systems, Sept. 2002

15.     VLSI Test Symp., FPGA Testing: Accomplishing the Impossible for ASICs, May 2002

16.     Texas A&M Univ., Built-In Self-Test of Mixed-Signal Microsystems and Programmable Logic, Apr. 2002

17.     Univ. of Kentucky, Built-In Self-Test of Mixed-Signal Microsystems and Programmable Logic, Mar. 2002

18.     Univ. of Porto, Portugal, On-Line and Off-Line BIST and Diagnosis of FPGAs, Nov. 2001

19.     Spotlight on Research (TV series), On-Line Testing and Fault Tolerance in Programmable Logic, Sept. 2001

20.     Agere Systems, Off-Line BIST and Diagnosis of FPGAs, Feb. 2001

21.     Cypress Semiconductor, Texas Design Center, Design for Testability, Sept. 2000

22.     Cypress Semiconductor, New England Design Center, Design for Testability, July 2000

23.     Cypress Semiconductor, Mississippi Design Center, Design for Testability, July 2000

24.     Cypress Semiconductor, Kentucky CAD Center, Design for Testability, July 2000

25.     Cypress Semiconductor, Colorado Design Center, Design for Testability, July 2000

26.     Cypress Semiconductor, Design for Testability, May 2000

27.     Lucent Technologies Engineering Research Center, A Mixed-Signal Based BIST Approach for Analog Circuits, Nov. 1998

28.     Lucent Technologies Engineering Research Center, Boundary Scan Access to BIST for FPGAs, Aug. 1998

29.     Cypress Semiconductor, Mixed-Signal Based Built-In Self-Test for Analog Circuits, Apr. 1998

30.     Lucent Technologies Engineering Research Center, Built-In Self-Test and Diagnosis of FPGAs, Mar. 1998

31.     Univ. of Illinois at Chicago, On-Line Built-In Self-Test for FPGAs, Mar. 1998

32.     Lucent Technologies, Built-In Self-Test and Diagnosis of FPGAs, Mar. 1998

33.     Cypress Semiconductor, Testability Analysis of CPLDs and FPGAs, Aug. 1997

34.     Oak Ridge National Laboratory, Built-In Self-Test and Diagnosis of FPGAs, June 1997

35.     Wright-Patterson AFB, Current Research in VLSI-FPGA Design & Test Laboratory, Mar. 1997

36.     Stanford Univ., Built-In Self-Test for Field Programmable Gate Arrays, Aug.1996

37.     LogicVision, Current Research in the VLSI/FPGA Design & Test Laboratory, Aug. 1996

38.     Synopsys, Improving the Effectiveness of Circular BIST in System Level Applications, Aug. 1996

39.     LogicVision, Current Research in the VLSI/FPGA Design & Test Laboratory, May 1996

40.     AT&T Bell Laboratories Engineering Research Center, Merging Concurrent Fault Detection Circuits with On-Line/Off-Line BIST, Dec. 1995

41.     IEEE Lexington Section Meeting, VLSI Design and Testing, Oct. 1995

42.     Army Research Laboratory, The Growing Relationship of Rapid System Prototyping and Design for Testability, July 1995

43.     AT&T Bell Laboratories, Built-In Self-Test for Field Programmable Gate Arrays, June 1995

44.     Vanderbilt Univ., Implementing Built-In Self-Test in ASICs, May 1993

45.     Univ. of Tennessee, Built-In Self-Test for Digital VLSI, Apr. 1993

46.     Univ. of Kentucky, Impact of VLSI Design on Product Development, Mar. 1993

47.     Tennessee Technological Univ., Digital VLSI Design and Testing, Nov. 1992

48.     Oak Ridge National Laboratory, Designing Built-In Self-Test for Digital Circuits, Aug. 1992

49.     National Soc. of Black Engineers, Region Conf., Nashville, TN, VLSI Design and Its Impact on Product Development, Oct. 1991

50.     Illinois Institute of Technology, Built-In Self-Test, Nov. 1990

51.     ACM/IEEE Design Automation Conf., Impact of Competing Implementation Media for ASICs, June 1990

52.     Lehigh Univ., Behavioral Model Synthesis, Oct. 1987

Note: invited presentations do not include faculty interviews or project reviews, other than those cases where a funding agency specifically asked for a presentation on something other than the research they were funding