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Description: aubist2 Description: Previous BIST Dudes & Dudettes

Topics

Recent Papers

Configurable

SoC

BIST

FPGAs: Excellent Platforms for SoC Testing R&D (ITC'08 – Elevator Talk)

BIST of Configurable Cores in SoCs Using Embedded Processor Dynamic Reconfiguration (ISoCC'05)

On-Chip BIST-Based Diagnosis of Embedded Programmable Logic Cores in SoCs (CATA'05)

Built-In Self-Test and Diagnosis of Multiple Embedded Cores in SoCs (ESA'05)

A System for Automated BIST of Embedded Memory Cores in System-on-Chip (SSST'05)

Embedded Processor Reconfiguration of Logic BIST for FPGA Cores in SoCs (NATW'05)

Built-In Self-Test for System-on-Chip: A Case Study (ITC'04)

FPGA

Logic

BIST

Built-In Self-Test of Embedded Memory Cores in Virtex-5 Field Programmable Gate Arrays (SSST'11)

Built-In Self-Test of Programmable Clock Buffers in Virtex-4, Virtex-5 and Virtex-6 FPGAs (SSST'11)

Built-In Self-Test for Multipliers in Altera Cyclone II Field Programmable Gate Arrays (SSST'11)

The First Clock Cycle is a Real BIST (ESA'10)

Soft-Core Embedded Processor-Based Built-In Self-Test of FPGAs: A Case Study (SSST'10)

Soft Core Embedded Processor Based Built-In Self-Test of FPGAs (DFTS'09)

Built-In Self-Test for Memory Resources in Virtex-4 Field Programmable Gate Arrays (CATA'09)

Built-In Self-Test of Configurable Logic Blocks in Virtex-5 FPGAs (SSST'09)

Built-In Self-Test of Digital Signal Processors in Virtex-4 FPGAs (SSST'09)

Embedded Processor-Based BIST and Diagnosis of Logic and Memory Resources in FPGAs (ESA'06)

BIST for Logic and Memory Resources in Virtex-4 FPGAs (NATW'06)

Built-In Self-Test of Virtex and Spartan II FPGAs Using Partial Reconfiguration (NATW'05)

On-Line BIST and BIST-Based Diagnosis of FPGA Logic Blocks (TVLSI'04)

FPGA

Routing

BIST

Built-In Self-Test of Global Routing Resources in Virtex-4 FPGAs (SSST'09)

Analysis and Evaluation of Routing BIST Approaches for FPGAs (NATW'07)

BIST-Based Delay-Fault Testing in FPGAs (JETTA'03)

BIST-Based Diagnosis of FPGA Interconnect (ITC'02)

FPGA

I/O

BIST

On System-Level Use of BIST for Programmable Input/Output Buffers in FPGAs (SECON'10)

Built-In Self-Test of Programmable Input/Output Tiles in Virtex-5 FPGAs (SSST'09)

Built-In Self-Test of Programmable I/O Cells in Virtex-4 FPGAs (NATW'08)

System-Level BIST for Programmable I/O Cells in FPGAs and SoCs (NATW'06)

Built-In Self-Test for Programmable I/O Buffers in FPGAs and SoCs (SSST'06)

Built-In Self-Test for I/O Buffers in FPGAs (NATW'05)

SEUs

in FPGAs

BIST of Embedded SEU Detection and Correction Cores in Virtex-4 and Virtex-5 FPGAs (ESA'09)

Embedded Processor Based Fault Injection and SEU Emulation for FPGAs (ESA'09)

Single Event Upset Detection and Correction in Virtex-4 and Virtex-5 FPGAs (CATA'09)

An Architecture for Fail-Silent Operation of FPGAs and Reconfigurable SoCs (ESA'06)

Mixed-Signal

BIST

 

Analog and

Mixed-Signal

Testing

Benchmark

Circuits

Automated Generation of BIST and Measurement Circuitry for Mixed-Signal Circuits and Systems (DFTS'09)

Test Time of Multiplier/Accumulator Based Output Response Analyzer in Built-In Analog Functional Testing (SSST'09)

FPGA-Based Analog Functional Measurement for Adaptive Control in Mixed-Signal Systems (TIE'07)

Noise Figure Measurement Using Mixed-Signal BIST (ISCAS'07)

Phase Delay Measurement and Calibration in Built-In Analog Functional Testing (SSST’07)

DDS-Based Mixed-Signal Built-In Self-Test (BIST) System (VFIS’07)

Automatic Linearity and Frequency Response Tests with Built-in Pattern Generator and Analyzer (TVLSI'06)

Analog Frequency Repsonse Measurement in Mixed-Signal Systems (ISCAS'06)

Phase Delay in MAC-Based Analog Functional Testing in Mixed-Signal Systems (NATW'06)

Built-In Self-Test for Automatic Analog Frequency Response Measurement (ISCAS'05)

Automatic Linearity (IP3) Test with Built-In Pattern Generator and Analyzer (ITC'04)

Other Design

and Test

On Built-In Self-Test for Multipliers (SECON'10)

PSIM: A Processor SIMulator for Basic Computer Architecture and Operation Education (SECON'10)

On Built-In Self-Test for Adders (JETTA'09)

Application of Embedded Systems in Low Earth Orbit for Measurement of Ionospheric Anomalies (ESA'09)

Built-In Self-Test for a Monobit Fast Fourier Transform Receiver (NATW'05)

 

The BIST Dudes & Dudettes:

 

The AUBIST Laboratory is a member of
Description: Alabama Microelectronics Science & Technology Center

 

Some recent accomplishments by the BIST Dudes & Dudettes:

Spring 2010: Jie Qin was named Auburn University Outstanding PhD Student for 2009-2010, Bill Tomas and Alex Lusco presented posters at the 7th Annual Undergraduate Research Forum

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Spring 2009: Brad Dutton was named Auburn University Outstanding MS Student for 2008-2009, Jie Qin was named Electrical & Computer Engineering Outstanding International Graduate Student, and Electrical & Computer Engineering Outstanding Faculty Member Award to C. Stroud

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July 2007: C. Stroud was Keynote Speaker at Cypress International Technical Conference

May 2007: IEEE North Atlantic Test Workshop Best Student Paper Award Honorable Mention went to Bobby Dixon

Spring 2007: College of Engineering Outstanding Coop Student Award to Mustafa Ali and College of Engineering William F. Walker Teaching Award for Excellence to C. Stroud

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AUBUST in the News

FPGA delay fault testing animation by John Sunwoo

Srinivas Garimella was named Auburn University Outstanding MS Student for 2004-2005.

Description: Srinivas Garimella named AU Outstanding MS Student for 2004-05

 

Description: AUBISTHappy BISTing!!!