The IEEE North Atlantic Test Workshop provides a forum for discussions on the latest issues relating to high quality, economical, and efficient testing methodologies and designs. With the increasing complexity in both design and test of integrated circuits and systems, the 17^th NATW features the dual themes: "Breaking Testing Barriers" and “Women in Test” with special presentations and a panel session dedicated to Women in Test. This year NATW includes 12 papers from 5 different companies and 19 papers from 13 different universities, including 17 student papers competing for the Jake Karrfalt Best Student Paper Award and the IEEE Boston Section NATW Student Fellowship Awards. In addition, the workshop includes a Special Session organized by the Vermont chapter of the Solid State Circuits Society. The 2008 workshop is held at the Holiday Inn at Boxborough, MA, and is sponsored, in part, by the Green Mountain Section of IEEE and the IEEE Women in Engineering Committee. NATW corporate/academic supporters for 2008 include Mentor Graphics, SynTest Technologies, Auburn University Dept. of Electrical and Computer Engineering, the Vermont chapter of IEEE Solid State Circuits Society, and the IEEE Boston Section.

Wednesday, May 14
6:30 - 7:30pm	Welcome Reception and Registration
7:30 - 9:00pm	Women in Test Panel Session: “Social and Professional Issues Women Face in the Field of VLSI Testing” Panel Chair: Linda Milor, Georgia Tech. Univ. Panelists: Daniela DeVenuto (Politecnico di Bari, Italy), Bozena Kaminska (Simon Fraser Univ.), Jen Miller (Intel), Karen Panetta (Tufts Univ.), Wenjing Rao, (Univ. Illinois - Chicago), Carol Stolicny (Intel)
Thursday, May 15
7:00 - 8:00am	Breakfast
8:00 - 8:15am	Opening Remarks: Sule Ozev (General Chair)
8:15 - 9:00am Keynote speaker introduction by Sule Ozev	Thursday Keynote Address: “Design and Test for Age Wave Applications” Bozena Kamiska, Simon Fraser Univ. Abstract: The approaching tsunami of the Baby Boomer Age Wave creates unprecedented demand for omnipresent technology woven invisibly into daily life to support health care, mobility, and independence — the “killer apps” of the 21st Century. Design and test face enormous challenges for safety-critical reliability and guaranteed functionality upon which life and death will literally depend. Hard lessons we learned — design for test, and test early test often — need to be applied across new fields of health care, medical devices, emergency communication, automobility, food and drug processing. To future shift our own careers, we need to adopt Shoshin, the Zen “Beginner’s Mind”, learning with openness and eagerness human biology to fruitfully apply our deepest technology. Illustrative examples from my own journey into wireless sensors and their safety-critical aspects for health and disease will be given.
9:00 - 9:10am	Short Break for Transition to Student Sessions
9:10 - 10:10am	Women in Test Student Session 1: Analog/Mixed-Signal Testing, Session Chair: Linda Milor
	1.1 “Parametric Fault Diagnosis for Analog Circuits Based on Neural Networks”, Z. Zhang* and S. Ozev (Duke Univ.) 1.2 “CATGEN: Circuit Analyzer and Test Generator”, B. Kim, S. Sundar* (Univ. Alabama), S. Wokhlu, E. Beskar, and R. Rousselin (Texas Instruments) 1.3 “Reconfigurable Delta-Sigma Based Analog-Digital Interface for the In-Field Test of Sensor Systems”, X. Cai*, A. Aleksanyan, E. Yilmaz, M. Brooke and S. Ozev (Duke Univ.)
10:10 - 10:30am	Coffee Break/Reception for Women in Test
10:30 - 11:50pm	Women in Test Student Session 2: Test Pattern Generation and Grading, Session Chair: Jennifer Dworak
	2.1 “Path-RO: On-Chip Critical Path Delay Measurement Under Process Variations”, X. Wang*, M. Tehranipoor (Univ. Connecticut), and R. Datta (Texas Instruments) 2.2 “RT-Level Grading of Functional Test Sequences”, H. Fang* and K. Chakrabarty (Duke Univ.) 2.3 “Test Pattern Generation For Open Defects in Power Distribution Networks”, J. Ma*, J. Lee, and M. Tehranipoor (Univ. Connecticut) 2.4 “Built-In Self-Test of Global Routing Resources in Virtex-4 FPGAs”, J. Yao*, B. Dixon, C. Stroud, and V. Nelson (Auburn Univ.)
12:00 - 1:00pm	Lunch
1:00 - 2:00pm	Student Session 3: Mixed-Signal Reliability and Test, Session Chair: Jim Monzel
	3.1 “A Substrate Noise Sensing Circuit for Noise Tolerance in Mixed-Signal Systems-on-a-Chip”, R. Wang, B. Brakus, H. Gopalakrishnan*, and J. Emmert (Wright State Univ.) 3.2 “Relay Reliability in the ATE Environment”, K. Kulovic*, R. Tilson, and M. Margala (Univ. Massachusetts – Lowell) 3.3 “Built-In Test and Calibration of DAC/ADC Using A Low-Resolution Dithering DAC”, W. Jiang* and V. Agrawal (Auburn Univ.)

2:00 - 3:00pm		Student Session 4: On-Line Test and Soft Errors, Session Chair: Ted Cooley
		4.1 “Using Implications for Online Error Detection”, N. Alves* (Brown Univ.), K. Nepal (Bucknell Univ.), J. Dworak and R. Bahar (Brown Univ.) 4.2 “A Field Analysis of Soft Errors Occurring in Microprocessors used in Information Systems”, S. Shazli*, M. Tahoori, and D. Kaeli (Northeastern Univ.) 4.3 “Probabilistic Soft Error Rate Estimation from Statistical SEU Parameters”, F. Wang* and V. Agrawal (Auburn Univ.)
3:00 - 3:10pm		Coffee Break
3:10 - 4:30pm		Student Session 5: Delay Faults and Built-In Self-Test, Session Chair: Xijiang Lin
		5.1 “Low-Power Transition-Delay Fault Pattern Generation”, J. Lee*, S. Narayan and M. Tehranipoor (Univ. Connecticut) 5.2 “Analyzing Reconvergent Fanouts in Gate Delay Fault Simulation”, H. Grimes* and V. Agrawal (Auburn Univ.) 5.3 “Sequential BIST Synthesis using Spectrum and Noise from ATPG Patterns”, N. Yogi* and V. Agrawal (Auburn Univ.) 5.4 “Built-In Self-Test of Programmable I/O Cells in Virtex-4 FPGAs”, B. Dutton*, L. Lerner, and C. Stroud (Auburn Univ.)
4:45 pm		Board bus to Social Program (winery tour, tasting, and dinner) and Best Student Paper Award
Friday, May 16
7:30 - 8:00am	Breakfast
8:00 - 8:45am	Friday Keynote Address: “Defects and Variability: A Call to Test from DFM” Anne Gattiker, IBM Abstract: Design-for-Manufacturability (DFM) is one of the biggest buzzwords in our industry today. Everyone agrees we need to design in such a way as to ensure our ICs can be manufactured successfully, but how do we choose from the myriad strategies we could apply? We must be guided by knowledge of the real manufacturing problems likely to occur and, importantly, by the impact those problems will have on the product. Test is uniquely suited to provide that knowledge, but must expand its capabilities to do so. This talk provides an evidence round-up looking at failure mechanisms in yesterday’s and today’s chips and discusses trends for the future, with an emphasis on manufacturing process variation. It argues for the vital, if often overlooked, role for test in guiding DFM and suggests ways test can rise to meet the challenge.
8:45 - 10:00am	Session 6: Special Session on Solid State Circuits & Systems Test, Session Chair: Pascal Nsame
	6.1 “Improving Memory BIST Value in a Tough Real Estate Market”, M. Ouellette*, M. Ziegerhofer, V. Chickanosky, S. Granato, P. Rachakonda, C. Mirashi, S. Jinagar and K. Gorman (IBM) 6.2 “Cost-Benefit Analysis for Functional Pattern Test Time Management”, M. Lee*, M. Grady, M. Johnson (IBM) 6.3 “On-Chip Circuit for Monitoring Degradation Due to NBTI”, K. Stawiasz*, K. Jenkins and P-F. Lu (IBM)
10:00 - 10:10am	Coffee Break
10:10 - 11:50pm	Session 7: Built-In Self-Test and Diagnosis, Session Chair: Mohammad Tehranipoor
	7.1 “A Built-In Test Circuit for Single Ended RF Low Noise Amplifiers”, L. Dermentzoglou (Univ. of Athens, Greece), Y. Tsiatouhas* (Univ. of Ioannina, Greece), A. Arapoyanni and A. Karagounis (Univ. of Athens, Greece) 7.2 “A Technique for Detecting Crosstalk Noise in FPGAs”, S. Kakarla and W. Al-Assadi* (Missouri Univ. of Science & Technology) 7.3 “The Effects of Space Compactors on Fault Diagnosis Resolution”, Y. Huang*, C. Wang, M. Sharma, G. Chen, WT Cheng (Mentor Graphics) and S. Reddy (Univ. of Iowa) 7.4 “Statistical Test To Uncover Process Variations”, V. Iyengar*, J. Xiong, S. Venkatesan, V. Zolotov, D. Lackey, P. Habitz and C. Visweswariah (IBM)
12:00 - 1:00pm	Lunch and Program Committee Meeting
1:00 - 3:05pm	Session 8: Scan-Based and N-Detect Test Techniques, Session Chair: Sule Ozev
	8.1 “Test Power Reduction by Blocking Scan Cell Outputs”, X. Lin* and J. Rajski (Mentor Graphics) 8.2 “Transition ATPG: An Important Tool in Post-Silicon Electrical Characterization”, P. Pant* and J. Zelman (Intel) 8.3 “Methodology for Automated Synthesis of IEEE 1500 Compliant Wrappers”, K. Chakravadhanula* and V. Chickermane (Cadence Design Systems) 8.4 “Dynamic N-Detect Patterns Based on Equivalent Faults”, P. Reuter* and Y. Huang (Mentor Graphics) 8.5 “Rapid Estimation of Post-Silicon Functional Test Coverage Using N-Detect Fault Grade Data”, M. Safer* and P. Pant (Intel)