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Wednesday, May 16 |
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6:30 - 7:30pm |
Welcome Reception and Registration |
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7:30 - 9:00pm |
Evening Panel Session: Coordinator and Moderator: Linda Milor, Georgia Tech. |
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Thursday, May 17 |
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7:00 - 8:00am |
Breakfast |
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8:00 - 8:15am |
Opening Remarks: Sule Ozev (General Chair) and Chuck Stroud (Program Chair) |
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8:15 - 9:00am |
Keynote Address: “In-System Silicon Validation and Debug – A New Look” by Dr. Miron Abramovici, DAFCA, Inc. |
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9:00 - 9:45am |
Invited Talk: “Architectural Vulnerability Factor (or Does a Soft Error Matter?)” by Dr. Shubu Mukherjee, Intel Corp. |
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9:45 - 10:00am |
Coffee Break |
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10:00 - 11:00am |
Student Session I: Scan Design and Test, Session Chair: Chuck Stroud |
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1.1 “A New Design-for-Test Technique to Enhance
Performance of Broadcast Scan-based Compressor”, Rajamani Sethuram* ( 1.2 “A Co-evolutionary Algorithm for Dynamic
Power Minimization During Scan Testing”, Alodeep Sanyal* ( 1.3 “SPARTAN: A Spectral and Information
Theoretic Approach to Partial Scan” Omar Khan* and Michael L. Bushnell ( |
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11:00 - 12:00pm |
Student Session II: Delay Testing, Session Chair: Jennifer Dworak |
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2.1 “High Coverage Delay Test with Partial
DTSFF Scan Chains”, Gefu Xu* and Adit D. Singh ( 2.2 “Combinational Hardware False Path
Identification without Search”, Gagandeep Sandha* Michael L. Bushnell and
Rajamani Sethuram ( 2.3 “Delay Fault Testing in Presence of Maximum
Crosstalk”, Jeremy Lee* and Mohammad Tehranipoor, ( |
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12:00 - 1:00pm |
Lunch |
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1:00 - 2:00pm |
Student Session III: New Research in Testing, Session Chair: Linda Milor |
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3.1 “Optimisation of IEEE 1500 Wrappers and
User Defined TAMs”, Michael Higgins*, Ciaran MacNamee and Brendan Mullane
(Univ. 3.2 “Optimizing Tests for Multiple Fault
Models”, Nitin Yogi* and Vishwani D. Agrawal ( 3.3 “A Graph Condensation Based Transitive
Closure Algorithm for Implication Graphs to Identify False Paths”, Rajamani
Sethuram* and Michael L. Bushnell ( |
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2:00 - 2:15pm |
Coffee Break |
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2:15 - 3:35pm |
Student Session IV: Testing Special Structures, Session
Chair: Vishwani Agrawal |
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4.1 “Improving the Bit-Error Rate Performance
of the Serializer-Deserializer (SERDES) Circuits with Jitter Reduction
Hardware”, Hari V. Venkatanarayanan* and Michael L. Bushnell ( 4.2 “Multi-Port SRAM Tests with Process
Variation Considerations”, Richa Hajela* and Xinghao Chen (City 4.3 “Analysis and Evaluation of Routing BIST
Approaches for FPGAs”, Bobby E. Dixon*
and Charles E. Stroud ( 4.4 “Wafer Level Loop-Back Test with
Out-of-Band Signals”, Erdem S. Erdogan* and Sule Ozev ( |
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4:00pm - ? |
Social Program:
Sight Seeing and Dinner in |
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Friday, May 18 |
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7:00 - 8:00am |
Breakfast |
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8:00 - 9:40am |
Session V: Delay Testing, Session Chair: Mike Bushnell |
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5.1 “At-Speed and ATE-Driven Delay Test of Contract-Manufactured ASICs”, Vikram Iyengar*, Kenneth Pichamuthu, Andy Ferko, Frank Woytowich, Dave Lackey,Gary Grise, Mark Taylor, Mike Degregorio and Steve Oakland (IBM Microelectronics and IBM Engineering & Technology Services) 5.2 “Delay Fault Testing of Interconnect Logic Between Embedded Cores”, Ramesh C. Tekumalla* (AMD, Inc.) 5.3 “IR-drop Tolerant Transition Delay Fault
Testing”, Nisar Ahmed, Mohammad Tehranipoor* ( 5.4 “High Resolution Delay Testing of
Interconnect Paths in Xilinx Virtex-4 FPGAs”, Jack Smith (IBM Corporation)
and Tian Xia*( |
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9:40 - 10:00am |
Coffee Break |
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10:00 - 11:40am |
Session VI: Scan Test and Power, Session Chair: Vikram Iyengar |
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6.1 “Reducing Test Cost and Power Consumption by Modular Embedded Deterministic Test (EDT) Flow”, David Hong, Fiona Zhou (Atmel Semiconductor), Wu Yang, Yu Huang* and Actel Niu (Mentor Graphics Corp.) 6.2 “On Identifying and Bypassing Faulty Scan Segments”, Ramesh C. Tekumalla* and Darin Lee (AMD, Inc.) 6.3 “Scan Shift Power Reduction by Freezing Power Sensitive Scan Cells”, Xijiang Lin* and Yu Huang (Mentor Graphics Corp.) 6.4 “Towards Universal Built-In Scan Structures
for ASIC Implementation Platforms”, Xinghao Chen (City |
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11:40 - 1:00pm |
Lunch |
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1:00 - 3:05pm |
Session VII: Debug the Test?, Session Chair: Chuck Stroud |
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7.1 “Test Set Optimization for Minimizing Field
Failure Rates due to Test Escapes”, Jennifer L. Dworak ( 7.2 “Clock-Data Race Aware Logic Diagnosis”, Yu Huang*, Wu-Tung Cheng and Ruifeng Guo (Mentor Graphics Corp.) 7.3 “Transitioning from Validation Environment and Content for Cache Resident Functional Test (CRFT)”, Andrew Angle* and Bryan Gran (Intel Massachusetts, Inc.) 7.4 “Modular Benefits of Hierarchical DFT: A Comprehensive Test Case”, Chris Tice, Joshua Zelman* and Rachana Shah (Intel Corp.) 7.5 “X-Cancelling – |