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2012 = Kemal Kulovic
(Univ. of Massachusetts - Lowell), “Flexible VITAL Embedded Instruments
for Built-In Test of AMS Power SOCs”
2011 = Marco Donato
(Brown Univ.), “Noise-Immune CMOS Circuits for Sub-Threshold Operation Using
Schmitt-Trigger Logic” (co-authors: K. Nepal, R. I. Bahar, W. Patterson, A. Zaslavsky,
and J. Mundy)
2010 = Zahra Lak
(McMaster Univ.), “A New
Algorithm for Post-Silicon Clock Measurement and Tuning”
(co-author: N. Nicolici)
2009 = Ke Peng (Univ. of Connecticut), “Efficient
Pattern Grading for Small Delay Defects in Digital Integrated Circuits”
(co-authors: M. Yilamaz, K. Chakrabarty,
and M. Tehranipoor)
2008 = Xiaoxiao Wang (Univ. of Connecticut), “Path-RO: On-Chip Critical Path Delay
Measurement Under Process Variations” (co-authors: M. Tehranipoor and R. Datta)
2007 = Alodeep Sanyal (Univ.
of Massachusetts),
“A Co-evolutionary Algorithm for Dynamic Power Minimization During
Scan Testing” (co-authors: A. Sokolov, Y. Malaiya and D. Whitley)
2006 = Nitin Yogi (Auburn Univ.),
“High-Level Test Generation for Gate-Level Fault Coverage” (co-author: V. Agrawal)
2005 = Jack Smith (Univ. of Vermont),
“Automated BIST Testing of Delay Faults in FPGA Interconnect” (co-author: T. Xiao)
2004 = Anuja Sehgal (Duke Univ.), “Cost-Oriented Test
Plan Development for Mixed-Signal SOCs with Wrapped Analog Cores” (co-authors: S. Ozev
and K. Chakrabarty)
2003 = Dan Zhao (SUNY-Buffalo), “A
New Distributed Test Control Architecture with Multiple Wireless Test
Connectivity and Communication for Gigahertz System-Chips” (co-authors: S. Upadhyaya, and M. Margala)
2002 = Lan Rao (Rutgers Univ.), “New Graphical Iddq Signatures Reduce Defect Level and Yield
Loss” (co-authors: M. Bushnell and
V. Agrawal)
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