VLSI Design & Test Seminar, Spring 2007




Transition Delay Fault Testing of Microprocessors by Spectral Method



Speaker:          Nitin Yogi, yoginit@auburn.edu

Date:               Wednesday, February 28, 2007

Time:               4:00 PM

Room:                         Broun 235





We introduce a novel spectral method of delay test generation for microprocessors at the register-transfer level (RTL). Vectors are first generated by an available ATPG tool for transition faults on inputs and outputs of the RTL modules of the circuit. These vectors are analyzed using Hadamard matrices to obtain Walsh function components and random noise levels for each primary input. A large number of vector sequences is then generated such that all sequences have the same Walsh spectrum but they differ due to the random noise in them. At the gate-level, a fault simulator and an integer linear program (ILP) compact these vector sequences. The initial RTL vector generation also reveals the hard-to-test parts of the circuit. An XOR observability tree was used to improve the testability of those parts. We give results for an accumulator-based processor named Parwan. The RTL technique produced higher gate-level transition fault coverage in shorter CPU time as compared to a gate-level transition fault ATPG.


This work will also be presented at the 39th Southeastern Symposium on System Theory (SSST), to be held in Macon, Georgia from March 4th to March 6th, 2007.