VLSI Design & Test Seminar, Spring 2007





Analyzing Reconvergent Fanouts in Min-Max Delay Fault Simulation




Speaker: Hillary Grimes, grimehh@auburn.edu

Date: Wednesday, March 14, 2007

Time: 4:00 pm

Room: Broun 235






Delay testing verifies that a manufactured VLSI design meets its speed requirements.  Min-Max delay fault simulation allows for process variations when simulating delay faults for accurate evaluation of test quality.  Most Min-Max delay fault simulation algorithms today lack fanout reconvergence analysis when certain time-correlations at the inputs of reconvergent gates can guarantee no hazard will occur at the output.  The result of incorrect hazard evaluation is pessimism in detectable delay fault sizes.  In this talk, we examine an event-driven technique that propagates hazard lists containing information about delay bounds from fanout points to correctly evaluate hazards.  Hazard list propagation is similar to fault list propagation in concurrent fault simulation.  Results for benchmark circuit c7552 show that 25% of critical gate delay faults are incorrectly assumed detected when correlations are ignored.  About 50% of critical gate delay faults are incorrectly assumed detected for c3540.  This research is performed in collaboration with Dr. S. Bose of Intel Corporation.