Delay Test Quality Evaluation Using Bounded Gate Delays
Speaker: Vishwani D. Agrawal
Date: Wednesday, April 11, 2007
Time: 4:00PM
Room: Broun 235
Abstract:
Conventionally,
path delay tests are derived in a delay-independent manner, which causes most
faults to be robustly untestable. Many non-robust
tests are invalidated by hazards caused primarily due to non-zero delays of
off-path circuit elements. Thus, non-robust tests are of limited value when
process variations change gate delays. We propose a bounded gate delay model
for test quality evaluation and give a novel simulation algorithm that is less
pessimistic than previous approaches. The key idea is that certain
time-correlations among the multiple transitions at the inputs of a gate cannot
cause hazard at its output. We maintain ``ambiguity lists'' for gates. These
are propagated with events, similar to fault lists in a traditional concurrent
fault simulation. They are used to suppress erroneous unknown states.
Experimental results for ISCAS benchmarks with gate delay variation of 14% show
a miscorrelation of critical path delay as much as 20%.
This
talk is based on a joint paper with Dr. Soumitra Bose
of Intel Corporation, to be presented at the 25th IEEE VLSI Test Symposium,