The VLSI Design & Test Seminar Series

seeks to provide an open forum for various faculty, graduate and undergraduate students with research and development efforts in the area of design and test of VLSI systems, including application specific and programmable circuits in digital, analog, and mixed-signal microsystems. The goal is to promote further learning, discussion, and teamwork along with the conception and development of exciting new ideas.

The seminar series counts as a 1-credit course ELEC7950 (which may be repeated for up to 3 credits).

 

This seminar series sponsored by:

the Testing Group at Auburn:

Vishwani Agrawal - Design for Testability (DFT) and low-power design

Foster Dai - mixed-signal and analog design and testing

Vic Nelson - ASIC/FPGA testing and fault tolerance

Adit Singh - digital and mixed-signal VLSI design and Design for Testability (DFT)

Chuck Stroud - digital and mixed-signal Built-In Self-Test (BIST)

 

Spring 2010 schedule:

When: Wednesdays from 4-5:30pm

Where: Broun Hall room 235

Coordinator: Chuck Stroud

Invitation: If you are interested in presenting a seminar or defending your thesis/dissertation, please contact the coordinator.

Notes: The following is a tentative schedule.  A link under Speaker is to an abstract of the presentation and a link under Topic is to a PDF file of the presentation slides.

Date

Speaker

Topic (w/ link to presentation slides after seminar date)

Jan 13

Chuck Stroud

AUBIST Mixed-Signal Built-In Self-Test and Measurement

Jan 20

George Starr

S-parameters Measurements with Mixed-Signal BIST & Mixed-Signal BIST Demonstration

Jan 27

Testing Group Faculty

Everything You Ever Wanted to Know About Graduate School But Were Afraid to Ask

Feb 3

Bradley Dutton

Embedded Soft-Core Processor-Based BIST for FPGAs (MS Thesis Defense)

Feb 10

Alex Lusco

PSIM: Processor Simulator (BS Honors Thesis Defense)

Feb 17

Testing Group Faculty

REU Students

NSF REU Program & Current Projects (plus meet the REU students)

Feb 24

Adit Singh

Chuck Stroud

Adapting to Adaptive Test: Adapting Test Basics (DATE presentation)

Soft-Core Embedded Processor-Based Built-In Self-Test of FPGAs: A Case Study (SSST presentation)

Mar 3

Vishwani Agrawal

Enhancing Random Access Scan for Soft Error Tolerance (SSST presentation)

Soft Error Considerations for Computer Web Servers (SSST presentation)

Mar 10

Zhang Yu

George Starr

Alex Lusco

An Algorithm for Diagnostic Fault Simulation (LATW presentation)

On Built-In Self-Test of Multipliers (SECON presentation)

PSIM: A Processor SIMulator for Basic Computer Architecture and Operation Education (SECON presentation)

Mar 17

No Seminar

Spring Break

Mar 24

George Starr

Built-In Self-Test for the Analysis of Mixed-Signal Systems (MS Thesis Defense)

Mar 31

Alex Lusco

Bill Tomas

A Built-In Self-Test Approach for Altera Multipliers (AUURF presentation)

Fault Simulatoin of Embedded Multiplier Built-In Self-Test (AUURF presentation)

Apr 7

Mary Pulukuri

Built-In Self-Test of Digital Signal Processor Cores in Virtex-4 and Virtex-5 Field Programmable Gate Arrays (MS Thesis Defense)

Apr 14

Qian Xi

Vishwani Agrawal

An Output Compression Scheme for Handling X-states from Over-Clocked Delay Tests (VTS presentation)

Application of Signal and Noise Theory to Digital VLSI Testing (VTS presentation)

Apr 21

Zhang Yu

A Diagnostic Test Generation System (NATW presentation)

Apr 28

Chuck Stroud

The First Clock Cycle is a Real BIST (ESA presentation)

 

Links to previous semesters of the VLSI Design & Test Seminar Series:

Fall 2009: Coordinator Vishwani Agrawal

Spring 2009: Coordinator Adit Singh

Fall 2008: Coordinator Chuck Stroud

Spring 2008: Coordinator Vishwani Agrawal

Fall 2007: Coordinator Adit Singh

Spring 2007: Coordinator Chuck Stroud

Fall 2006: Coordinator Adit Singh

Spring 2006: Coordinator Vishwani Agrawal

Fall 2005: Coordinator Chuck Stroud

Spring 2005: Coordinator Adit Singh

Fall 2004: Coordinator Chuck Stroud