The VLSI Design & Test Seminar Series
seeks to provide an open forum for various faculty, graduate and undergraduate students with research and development efforts in the area of design and test of VLSI systems, including application specific and programmable circuits in digital, analog, and mixed-signal microsystems. The goal is to promote further learning, discussion, and teamwork along with the conception and development of exciting new ideas.

The seminar series counts as a 1-credit course ELEC7950 (which may be repeated for up to 3 credits).

This seminar series sponsored by:

the Testing Group at Auburn:

Vishwani Agrawal - Design for Testability (DFT) and low-power design

Foster Dai - mixed-signal and analog design and testing

Vic Nelson - ASIC/FPGA testing and fault tolerance

Adit Singh - digital and mixed-signal VLSI design and Design for Testability (DFT)

Chuck Stroud - digital and mixed-signal Built-In Self-Test (BIST)

Spring 2007 schedule:

When: Wednesdays from 4-5:30pm

Where: Broun Hall room 235

Coordinator: Chuck Stroud

Invitation: If you are interested in presenting a seminar during Spring 2007, please contact the coordinator.

Notes: The following schedule was for Spring 2007. The link under Speaker is to an abstract of the presentation and the link under Topic is to a PDF file of the presentation slides.

Date	Speaker (w/ link to abstract)	Topic (w/ link to presentation slides after seminar date)
Jan. 10	J-M Wersinger, COSAM	AUSSP and Space Radiation Damage to Satellite Electronics
Jan. 19	Joe Bungo, ARM	The ARM CPU Architecture
Jan. 24	Lee Lerner	Fail-Silent and TMR Architectures for FPGAs and Configurable SoCs
Jan. 31	Chuck Stroud	FPGA Architectures and Operation for Tolerating Single Event Upsets
Feb. 7	Chris Erickson	Test Pattern Generation for DSP BIST in Virtex-4
Feb. 14	Testing Group Faculty	Graduate School Research & Expectations – St Valentine’s Day Massacre
Feb. 21	Jie Qin	BIST-Based Phase Delay Measurements in Mixed-Signal Systems (SSST paper)
Feb. 28	Nitin Yogi	Transition Delay Fault Testing of Microprocessors by Spectral Method (SSST paper)
Mar. 7	Chuck Stroud	AUSIM: A Simulator for Research and Education Link to AUSIM
Mar. 14	Hillary Grimes	Analyzing Reconvergent Fanouts in Min-Max Delay Fault Simulation
Mar. 21	Vic Nelson	The Cypress Programmable System-on-Chip (PSoC)
Apr. 4	Daniel Milton	BIST for Block RAMs in Virtex-4 FPGAs
Apr. 11	Vishwani Agrawal	Delay Test Quality Evaluation Using Bounded Gate Delays (VTS paper)
Apr. 18	Nitin Yogi Gefu Xu Bobby Dixon	Optimizing Tests for Multiple Fault Models (NATW paper) High Coverage Delay Test with Partial DTSFF Scan Chains (NATW paper) Analysis and Evaluation of Routing BIST Approaches for FPGAs (NATW paper)
Apr. 26	Gefu Xu	Delay Test Scan Flip-Flop Design and Application for Scan Based Delay Testing (PhD Proposal)
May 4	Nitin Yogi	Gate-level Test Generation using Spectral Methods at Register Transfer Level (PhD Proposal)
May 21	Yuanlin Lu	Power and Performance Optimization of Static CMOS Circuits with Process Variation (PhD Defense)

Links to previous semesters of the VLSI Design & Test Seminar Series:

Fall 2006: Coordinator Adit Singh

Spring 2006: Coordinator Vishwani Agrawal

Fall 2005: Coordinator Chuck Stroud

Spring 2005: Coordinator Adit Singh

Fall 2004: Coordinator Chuck Stroud