The VLSI Design & Test Seminar Series
seeks to provide an open forum for various faculty, graduate and undergraduate students with research and development efforts in the area of design and test of VLSI systems, including application specific and programmable circuits in digital, analog, and mixed-signal microsystems. The goal is to promote further learning, discussion, and teamwork along with the conception and development of exciting new ideas.

The seminar series counts as a 1-credit course ELEC7950 (which may be repeated for up to 3 credits).

This seminar series sponsored by:

the Testing Group at Auburn:

Vishwani Agrawal - Design for Testability (DFT) and low-power design

Foster Dai - mixed-signal and analog design and testing

Vic Nelson - ASIC/FPGA testing and fault tolerance

Adit Singh - digital and mixed-signal VLSI design and Design for Testability (DFT)

Chuck Stroud - digital and mixed-signal Built-In Self-Test (BIST)

Fall 2008 schedule:

When: Wednesdays from 4-5:30pm

Where: Broun Hall room 235

Coordinator: Chuck Stroud

Invitation: If you are interested in presenting a seminar during Fall 2008, please contact the coordinator.

Notes: The following is a tentative schedule for Fall 2008. The link under Speaker is to an abstract of the presentation and the link under Topic is to a PDF file of the presentation slides.

Date	Speaker	Topic (w/ link to presentation slides after seminar date)
Aug. 20	The Testing Group	An Informal Get Together for Students and Faculty to Meet Each Other and Discuss Research Areas and Interests
Aug. 27	AUBIST Lab	Production System-Level Use of Built-In Self-Test for Virtex-4 & Virtex-5 FPGAs
Sept. 3	Jins Alexander	Simulation Based Power Estimation for Digital CMOS Technologies (MS Defense)
Sept. 10	Testing Group Faculty	Everything You Ever Wanted to Know About Graduate School But Were Afraid to Ask
Sept. 17	Adit Singh	Scan Delay Testing of Dual/Multi Core Processors for Small Delay Defects (ITC presentation)
Sept. 26	Sperby Piner, ADTRAN	VLSI and FPGA Design for Communications Equipment at AdTran
Oct. 1	Chuck Stroud	FPGAs: Excellent Platforms for SoC Testing R&D (ITC presentation)
Oct. 8	Wei Jiang	Built-in Self-Calibration of On-chip DAC and ADC (ITC presentation)
Oct. 15	Robert Chua, NVIDIA	Mixed-Signal Testing and Production Test at NVIDIA
Oct. 22	Nitin Yogi	Data Mining Approach for C65 Silicon Timing Mismatch Investigation
Oct. 29	No Seminar	International Test Conference Week
Nov. 5	Nitin Yogi	Sequential Circuit BIST Synthesis using Spectrum and Noise from ATPG Patterns (ATS presentation)
Nov. 12	Bradley Dutton	SEU Detection and Correction in FPGA Configuration Memories
Nov. 19	Chuck Stroud	SEU-Tolerant Design Approaches for FPGAs
Nov. 26	No Seminar	Thanksgiving Break
Dec. 3	Khushboo Sheth	A Hardware-Software Processor Architecture using Pipeline Stalls for Leakage Power Management (MS Defense) plus Seminar Evaluation Forms

Links to previous semesters of the VLSI Design & Test Seminar Series:

Spring 2008: Coordinator Vishwani Agrawal

Fall 2007: Coordinator Adit Singh

Spring 2007: Coordinator Chuck Stroud

Fall 2006: Coordinator Adit Singh

Spring 2006: Coordinator Vishwani Agrawal

Fall 2005: Coordinator Chuck Stroud

Spring 2005: Coordinator Adit Singh

Fall 2004: Coordinator Chuck Stroud