11. Final Exam Scope

The class final exam will be open book, open notes, open computer, and open Internet. The problems will mainly come from our notes and homework assignments. For instance, you may be asked to explain how halo doping affects the threshold voltage versus gate length curve, or how threshold voltage choice affects the Ion and Ioff of a MOS transistor, or how multiple cores help with performance/power trade-off.

A list of topics are given below for you to prepare for the final exam. You can refer to the journal and HTML notes (posted on blackbaord and this HTML site respectively), our text book, and use IEEE explorer for exam preparation.

We will address all of these issues in more depths next semester, Spring 2012, in ELEC7710, Field Effect Transistor, where we will also address physics based compact modeling, TCAD (in 6710, I have basically provided existing codes for you to use, you will learn how to write your own codes, including building 2d and 3d devices in 7710), RF and microwave properties, including noise and linearity, CMOS low-noise amplifier design, as well as on-wafer characterization using automatic probe station and ICCAP which you have seen in my lab towards the end of the semester, using state-of-the-art CMOS and SiGe BiCMOS wafers. As you may have noted from taking 6710, I generally emphasize hands-on experience in my teaching and will work closely with you on derivation, Matlab/Python coding, TCAD coding / demonstration, as well as Spice/Ads/Cadence tools.

11.1. Band diagrams

Draw PN junction as well as MOS capacitor band diagrams. Should be able to identify accumulation, depletion, inversion, strong inversion. Reviewing relevant notes, journal as well as HTML, will be sufficient.

11.2. Field Effect

Draw surface potential, total charge, and inversion charge as a function of gate voltage. Identify the different operation regions on all of these curves, e.g. accumulation, depletion, inversion, or strong inversion.

You can use existing homework matlab codes to draw these graphs instead of by hand.

11.3. Threshold voltage

Calculate both gate to body and gate to channel (or source) threshold voltage for given gate material, substrate doping and oxide thickness, at different channel to body bias (Vcb).

Reviewing the notes on 3 terminal MOS should be sufficient.

11.4. Internal potential and field

For a long channel MOSFET, sketch how surface potential, inversion charge density, depletion thickness, lateral electric field and electron velocity vary from source to drain at the following biases:

  1. Vg << Vth, Vds=0
  2. Vg > Vth, Vds < Vdsat
  3. Vg > Vth, Vds > Vdsat

You only need to sketch the region from source to the “pinch-off” point. Velocity saturation can be neglected.

11.5. Velocity saturation

How does it affect electron velocity along the channel? How does it impact Id-Vd curves?

Why is velocity saturation more important in shorter channel devices?

11.6. Subthreshold swing (SS)

Understand its definition and how it affects the choice of threshold voltage to achieve a given off current (e.g. Id at Vg=0 has to be less than 1nA, if S=100 mV/decade, what value of Vth should you need in transistor design).

What is the smallest SS one can achieve?

For an ideal long channel MOSFET, if the surface potential increases by 0.9mV per 1mV gate voltage increase, what will the SS be?

11.7. Ion and Ioff

Understand what determines Ion and Ioff.

For instance, for a transistor with Vt=0.3V, SS = 90mV/decade, W=90nm, L=45nm, estimate its 1) Ioff, defined as Id at Vg=0V, and 2) subthreshold Id at Vg=0.15V.

Reviewing the journal note on subthreshold current should be sufficient.

11.8. Short channel effect

Explain how scaling gate length affects threshold voltage.

11.9. DIBL

Understand DIBL effect and its measure. Use tecplot_sv to illustrate how DIBL effect varies with channel length and how it is affected by halo doping in short channel devices.

11.10. Effect of Halo Doping

Explain the effect of halo doping on transistor Id-Vg, Vth-lgate using tecplot_sv. Simulated potential contours with and without halo need to be well understood.

11.11. Channel length scaling limit

Minimum channel length one can achieve highly depends on gate oxide thickness or equivalent gate oxide thickness and device structure, e.g. a tri-gate vs traditional bulk.

Many of the Id-Vg curves you see in textbooks show real bad short channel behavior at gate length of 0.25um. While at the same gate length, in the simulations you have been running, the Id-Vg is ideal and long channel like.

This is mainly because of the difference in oxide thickness.

Historically, the short channel length limit was thought to be 500nm in the 70s, 250nm in the 80s, 100nm in the 90s when I was in grad school, and now 22nm is in production.

So the channel length scaling potential was vastly underestimated, primarily because our ability to make transistor quality thin oxide was underestimated.

11.12. Metal gate, high K

Why metal gates and high K gate dielectric are used in modern CMOS.

11.13. FinFETs, Tri-gate, Nanowire FETs

Such structures are all aimed at increasing gate control over the whole Si channel volume which help keeping subthreshold swing (SS) close to ideal. DIBL is minimized and sub-surface leakage found in bulk even regular SOI MOSFETs are suppressed.

11.14. Vdd Scaling and Multi-core Processing

Power consumption in CMOS is primarily due to switching. P = C Vdd^2 f. A key point to take away from this equation we derived is that power consumed is not linearly proportional to Vdd, rather, it is proportional to the square of Vdd. This may sound counterintuitive at first, but is satisfying if you think about the capacitive nature of the load in CMOS logic circuits. The charging current dQ/dt on average is also proportional to Q, which is CVdd, leading to the square of Vdd dependence.

Instead of running 1 core at full Vdd and full speed (f), we could run multiple cores at a reduced Vdd and a correspondingly reduced frequency. You should be able to quantify the advantages of such approach in power consumption as well as throughput. Multi-core processing also facilitates power management as individual cores can be turned on and off. See the journal notes for a numerical example.

11.15. CMOS Layout Basics

Multi-finger layout for reducing gate resistance and signal delay.

11.16. Analog Amplifiers

How does the gm * Rout product change with scaling? What is the typical gm*Rout number in 45nm and 32nm CMOS?

11.17. Drain Current Thermal Noise

What is the PSD of drain current noise of a MOSFET in sub-threshold region? How does it compare to 2qIDS with IDS being the dc biasing current?

Above threshold voltage, in saturation region, is the drain current noise smaller or larger than 2qIDS?