VLSI Design and Test Seminar

"Improving CMOS Open Defect Coverage Using Hazard Initialized Tests"

Chao Han
ECE Doctoral Candidate

Wednesday, March 26, 2014
4:00 pm, 235 Broun Hall


Abstract: 
Recent studies indicate that a significant number of very large delay faults that increase circuit path delays several fold, remain difficult to detect and are only discovered by very carefully crafted and comprehensive two-pattern tests, e.g. cell aware tests. A likely source of such large delays in CMOS is stuck-open faults. It is well known that many open faults are not covered by commonly employed TDF launch on capture (LOC) scan delay tests; the coverage of specially generated transistor stuck-open tests published in the literature is only modestly better. It is commonly assumed that such undetected open faults are benign because the circuit states needed to activate them cannot be reached in normal functional operation. In practice CMOS circuits experience many more transient states from the large number of hazards that occur during switching transitions. Many undetected open defects can still be activated by such hazards during normal operation and cause a functional error. Such open faults must be detected by tests targeting low DPPMs. In this paper we present an ATPG based delay test methodology to target a key class of such hazard initialized open faults that are not detected by traditional stuck open tests.