create testbench symbol

software: design architect;

input: s1238_testbench.vhd;

output: s1238_testbench_sb symbol

see file tree

TestBench is just another Verilog/VHDL program with built-in circuit test pattern generation capability. It reads back the output responses of the circuit under test (CUT) and decides whether the CUT meets the specifications.

1)compile qsim_logic.vhd

-cp /opt/modeltech/vhdl_src/mentor/qsim_logic.vhd .

-vlib work

-vmap work work

-vcom qsim_logic.vhd

2)compile vhdl file

-copy s1238_testbench.vhd to ...user folder/s1238/

-vlib work

-vmap work work

-compile s1238_testbench.v with command "vcom s1238_testbench.vhd -qspro_syminfo"

*Note:

vlib phy_lib_path;

vmap logical_lib phy_lib_path;

These information is saved in the modelsim.ini file

3)create symbol

-create a folder to save symbol (.../s1238/work/s1238_testbench_sb)

-run design architect (with command "da" or "adk_da")

-generate symbol

-check symbol

-save symbol