generate schematic

software: edif2eddm

input: s1238_scan.edf

output: a "./work/s1238 folder" which save a set of schematic files

see file tree

Now we have the final verilog file that includes the scanned memory elements. The next step is to generate the schematic that is used for design architecture. Mentor Graphics provides a script file “EDIF2EDDM” that accomplishes this functionality. After successful translation, the circuit is able to be shown in a circuit level schematic.

-use edf file generate schematic (use command "edif2eddm s1238_scan.edf")

-view s1238 schematic

-download s1238 schematic

(If you print your schematic sheet in "Design Architect", the sheet will print to a ps file under the folder "/opt/idea_EN/users/yourname.ps")

-generate viewpoint for schematic (use command " adk_dve s1238_verilog ami05",s1238_verilog is the fold saving schematic. Note the parameters are dependent on technology on which that the design is going to be fabricated. )