generate scan edif file
input: s1238_scan.v, setup.tcl;
purpose: generate edif file with scan chains.
Now we can generate the EDIF file based on the scanned version circuit Verilog description. EDIF serves as one of the standard file format to ease the data exchange. There are some new approaches that actually don't depend on generating this intermediate file, such as "silicon compilation". But to follow the "traditional" style ASIC design flow. This effort is still exercised.
see file tree
-copy setup.tcl to your work folder
2)generate scan edif file
-run leonardo (command "leonardo")
-Run script: setup.tcl
(the steup file tells the desired parameters in this process, such as the limit of fan-outs, etc. )
-load library (ASIC/ADK/AMI 0.5 micron fast)
-read verilog file (s1238_scan.v)
(This includes the optimizations for power, delay and/or area. )
-output edif file (s1238_scan.edif)