generate scan verilog file

software: dftadvisor

input: s1238_opt.v, dft.map;

output: s1238_scan.v

purpose: generate verilog file with scan chains.

(This step generates the scanned version of the verilog file. Basically the tool will analyze the circuit structure and finds the memory elements (DFFs) and replaces these elements using scanned version. )

see file tree

1)prepare work

-copy dft.map to your work folder

2)generate scan verilog file

-run dftadvisor (command "dftadvisor -verilog s1238_opt.v –lib $ADK/technology/adk.atpg")

    (if you use vhdl file you should use command "dftadvisor -vhdl s1238_opt.vhd -lib $ADK/technology/adk.atpg")

-in "SETUP" command window use command "set system mode setup" >> " add clocks 0 /CK" >>analyze control signal >> set system mode dft >> run >> insert test logic

-save result (s1238_scan.v)

-in "SETUP" command window input "exit"